US5255215A - Digital filter system with changeable cutoff frequency - Google Patents

FIG. 22 shows a storage map of the

1 in FIG. 21;

FIG. 23 is a table showing operation of the adder/

16 in FIG. 21;

FIG. 1 shows an overall arrangement of an electronic musical instrument incorporating a digital filter system in accordance with a first embodiment of the invention.

101 controls the entire system.

102 stores program instructions executed by

101. Coefficient ROM stores filter coefficients corresponding to each of a plurality of discrete cutoff frequencies.

104 serves as a working memory for

101.

105 provides performance input to the musical instrument in a conventional manner.

106 is used to variably input a desired cutoff frequency in an analog form which is digitized by a digital to analog converter not shown.

107 generates a tone signal(s). Digital filter (DF) 108 filters the tone signal from the

107. The filtered tone signal is sounded out through an

109 and a

110.

By way of example, the

108 may take the form of a second order infinite impulse response (IIR) filter. FIG. 2 shows a logical arrangement of each IIR filter.

In FIG. 2, the digital filter comprises

201 to 205, one-

206 to 209 and an adder (summer) 210, coupled as shown. Certain filter coefficients vary depending on the cutoff frequency and they include; coefficient K of the

201 for multiplying an input signal (tone signal from the tone generator 107), coefficient b1 of the first order feed-

202 and coefficient b2 of the second order feed-

203. More specifically, as indicated in FIG. 2, these coefficients b1, b2 and K are given by:

FIG. 3 depicts the dependencies of coefficients b1, b2 and K on the cutoff frequency in the range of fc/fs=0 to 0.5 according to the formula above. If the coefficients were stored for all possible values of the cutoff frequency commanded from the volume K, this would requre an enormous storage capacity. In accordance with the invention, the

103 is designed to store only those filter coefficients at (more) discrete cutoff frequencies. In addition, an interpolation technique is applied to obtain coefficients at a cutoff frequency between the stored discrete cutoff frequencies. Since coefficient K is easy to calculate from coefficients b1 and b2 as K=(1+b1+b2)/4, storage of only coefficients b1 and b2 in

106 will suffice.

FIG. 4 shows a storage allocation of the

103 in the case of nine discrete cutoff frequency samples. (A-b1) represents the start address of b1 coefficient memory while (A-b2) denotes the start address of b2 coefficient memory. Let an analog to digital converter (not shown in FIG. 1) for digitizing the analog output from the volume indicative of a desired cutoff frequency have a quantizing resolution of eight bits so that all possible values of the (digitized) desired cutoff frequency range from 0 to 127, totalling 128 in number. Then, for nine discrete cutoff frequency samples, adjacent addresses of the

103 have an equivalent spacing (frequency difference) which is sixteen times the quantized difference of the desired cutoff frequency. In FIG. 4, each stored coefficient symbol (b1, b2) is followed by a number which indicates a cutoff frequency value in hexadecimal notation. Thus "b110H", for example, means a coefficient b1 at a cutoff frequency value of 10H. Therefore, the highest four bits of an 8-bit desired cutoff frequency supplied from the

106 through the analog to digital converter constitute an integer part that determines a relative address of each coefficient memory while the lowest four bits indicate a fractional part.

FIG. 5 shows a main flow of

101. Upon power-on,

101 initializes the system (7-1) and the digital filter (DF) 108 (7-2). After the

101 repeatedly executes the main loop (7-3 to 7-5). The main loop includes Control DF routine 7-4 as well as other processes 7-3 and 7-5 required for the musical instrument.

FIG. 6 shows a flow chart of the Initialize DF routine 7-2. This routine first reads from the volume 106 a (digitized) value of the desired cutoff frequency at the power-on time, as VOL in the range of 0 to 127, and loads VOL into C register for initialization (8-1). C register serves as goal or reference storage means for storing a goal or reference value of operative cutoff frequency of the

108. Then, block 8-2 interpolates (calculates) filter coefficients at the value C of the cutoff frequency fc, using the

103 in a manner to be described later in accordance with a flow chart of FIG. 8, and transfers the interpolated coefficients as current filter coefficients to the

108.

FIG. 7 shows a detailed flow chart of Control DF routine 7-4. The function of this routine is to calculate a new goal (subgoal) of the cutoff frequency in response to a new value of the desired cutoff frequency from the

106 and to obtain filter coefficients at the new goal of the cutoff frequency.

To this end, Control DF routine first executes block 9-1 to read a new value VOL of the desired cutoff frequency from the

106. If the new value VOL is equal to the reference value (old goal) C of the operative cutoff frequency (9-2), Control DF routine directly terminates because there is no need for updating the goal (i.e., creating a new goal) of the operative cutoff frequency. If VOL differs from C, block 9-3 measures the difference ΔVOL by subtracting the old goal C from the new desired cutoff frequency VOL. Block 9-4 compares the absolute value |ΔVOL| of the difference with a

20H. This

20H corresponds to address distance of 2 in the

103 in FIG. 4, and indicates a relatively small difference of cutoff frequency.

If the new value VOL of the desired cutoff frequency is sufficiently close to the old goal C (20H≧|ΔVOL|), Control DF routine executes block 9-5 to update the goal C equal to the new value VOL from the

106.

On the other hand, if the new desired cutoff frequency VOL differs from the old goal C by more than the

20H, Control DF routine creates a new goal (subgoal) of the cutoff frequency that is not equal to the new (and greatly changed) desired cutoff frequency but is located between the old goal value C and the new desired value VOL. To this end, block 9-7 checks the sign of the difference ΔVOL to see which one of the old goal value C and new desired value VOL is larger than the other. Depending on the sign, either block 9-8 or 9-9 is executed to create a new goal C of cutoff frequency by changing the old goal C by 20H in such a manner that the new goal is directed toward the new value VOL of the desired cutoff frequency.

FIG. 8 shows a detailed flow chart of the Interpolate Coefficients routine 9-6. In brief, this routine interpolates filter coefficients at the new goal value of digital filter cutoff frequency based on or as a function of those filter coefficients stored in the

103 and near the new goal of the cutoff frequency. In the case of FIG. 8, each filter coefficient at the new goal of cutoff frequency is linearly interpolated by calculating a linear function of a pair of stored coefficients at adjacent discrete cutoff frequencies nearest to the new goal value of the cutoff frequency.

In summary, Control DF routine (FIG. 7) can control the

108 without deteriorating its characteristics. Even if the desired cutoff frequency input from the

106 is greatly changed, the Control DF routine repeatedly operates in the main loop (see FIG. 5) to produce a succession of subgoals of digital filter cutoff frequency that progressively approaches the changed desired cutoff frequency. The difference between successive subgoals is only a small one. Each time when it creates a new subgoal of cutoff frequency, Control DF routine interpolates filter coefficients at the new subgoal, using stored filter coefficients in

103.

FIGS. 9 to 11 depict evaluations of the interpolated results obtained from the process shown in FIG. 8. In particular, FIG. 9 shows pole movements (pole loci) on Z plane of the second order IIR digital low pass filter in FIG. 2. Curve B is a pole movement obtained with an ideal filter of Butterworth type that uses direct calculations of b1, b2 and K coefficients according to the formula indicated in FIG. 2. Curve B is an interpolated pole movement obtained with linear interpolated coefficients resulting from the process of FIG. 8, starting with nine stored samples in the

103. Nine pole points corresponding to the nine discrete cutoff frequency samples are indicated in FIG. 9 by a8 to i8 with their fc/fs ratios ranging from 0.01 to 0.49. In particular, fc/fs ratio of pole point a8 is 0.01, that of b8 is 0.07 and so on with the leftmost pole point i8 having fc/fs of 0.49. Interpolating between each two adjacent pole samples results in the curve A. The interpolated pole locus A moves outward of the ideal pole locus B.

In addition to the background program shown in FIG. 5, the

102 stores a time interrupt routine which is periodically executed by

101 per 5 milliseconds. The time interrupt routine references filter coefficients b1, b2 and K from Control DF routine 7-4 (FIG. 7) in the main loop of the background program to calculate changing rates of the coefficients and send them to the

108 together with the filter coefficients.

FIG. 13 shows a flow chart of the time interrupt routine. Block 15-1 gets b1, b2 and K coefficients (here denoted by Tb1, Tb2 and TK) from the Control DF routine. These coefficient values Tb1, Tb2 and TK indicate a new goal (subgoal) of the coefficients where the

108 will reach. Block 15-2 calculates respective differences Δb1, Δb2 and ΔK between the new goal of the coefficients Tb1, Tb2 and TK, and the current value of the coefficients Cb1, Cb2 and CK as:

Block 15-3 calculates a predetermined fraction of each difference Δb1, Δb2 and ΔK to obtain a changing (interpolating) rate of each coefficient, denoted hrb1, hrb2 and hrK. Let, here, 32 microseconds be the interpolation period of the

108 interpolator which updates or changes the operative filter coefficients of the digital filter by the changing rates. Then, for a 5 millisecond period of parameter transfer from

101 the

108 interpolator can update the operative filter coefficients up to 156 times. Considering a margin, if 1/128 is chosen as the fraction above, the operative coefficients of the

108 will reach the subgoal before a new subgoal of the coefficients is supplied from

101. Thus, the block 15-3 shifts right Δb1, Δb2 and ΔK by 7 bits, which is equivalent to multiplying Δb1, Δb2 and ΔK by 1/128, to obtain coefficient changing rates hrb1, hrb2 and hrK. Block 15-4 send the digital filter 108 a new set of parameters comprising Tb1, Tb2, TK, hrb1, hrb2, and hrK. Finally block 15-5 moves Tb1, Tb2 and TK to current registers Cb1, Cb2 and CK, respectively.

FIGS. 14 and 15 show how the cutoff frequency of the digital filter changes with time. FIG. 14 is the case in which a fixed changing rate (differential value) of each coefficient is supplied to the digital filter from

101 per each 5 milliseconds. In the case of FIG. 15, a changing rate of each coefficient supplied from

101 is variable in proportion to the difference between the old and new subgoals of the coefficient. Such variable changing rate is obtained in accordance with the flow chart of FIG. 13. With a fixed changing rate, the time required for the digital filter to reach a new subgoal of the cutoff frequency varies depending on the difference between the old and new subgoals. Thus, the operative cutoff frequency v.s. time profile takes the form of a staircase as shown in FIG. 14. This results in an unsmooth variation in the characteristics of the tone signal filtered through the

108. In contrast, DF control using variable coefficient changing rates in proportion to intersubgoal difference provides a smooth variation in the operative cutoff frequency of the

108, as shown in FIG. 15, because the time for the

108 to move from one subgoal to another is kept essentially constant.

It is preferred that the desired cutoff frequency from the

100 is represented by value in proportion to cent. It is also preferred to allocate filter coefficients in

103 the cutoff frequency of which is proportional to cent in order to facilitate addressing the

103.

FIG. 17 shows three different relationships between

103 address and cutoff frequency. Lines M and N are examples in which cutoff frequencies assigned to addresses are directly proportional to cent (i.e., the cutoff frequency difference between adjacent addresses is a pretermined number of cents). Curve L is obtained when those cutoff frequencies which minimize the interpolation error are assigned to the coefficient ROM addresses.

Using the cent-proportional scheme, as depicted in lines M and N, it becomes easier to calculate from the desired cutoff frequency the coefficient ROM address that stores a filter coefficient at or near the desired cutoff frequency commanded from the

106. In addition, the cent-proportional scheme provides a linear relationship between amount of manipulation of a manipulator such as

106, and desired cutoff frequency, which relationship is linearly perceived or heard. Accordingly it becomes easier for the user to command any desired cutoff frequency.

FIG. 18 is a block diagram illustrating the main portion of the second embodiment. FIG. 19 shows a basic arrangement of the

301 in FIG. 18.

The illustrated digital filter system, which may be applied to an electronic musical instrument, basically comprises a

300,

302 and an

301. The

300 may be either a single or multiple signal processing digital filter.

302 defines control means for controlling the digital filter. The

301 provides an interface between

302 and the digital filter.

302 operates asynchronous with the

300. In particular,

302 repeatedly produces and supplies a set of parameters including filter coefficients and their changing rates (differential values) at a relatively slow sampling rate. The

300 produces filtered signal output samples at a relatively high sampling rate which must be kept constant for certain applications.

The

301 is designed to produce, on a time divisional multiplexing basis, a plurality of interpolated (operative) filter coefficients based on the set of parameters from

302 per each sampling cycle of the digital filter for each signal to be processed. For example, if a second order infinite impulse response (IIR) filter shown in FIG. 20 is chosen as (each channel of) the

300, the

301 produces three filter coefficients b1, b2 and K for each signal per each filter sampling cycle. To produce these operative filter coefficients, the

301 uses the set of parameters supplied from

301. The set of parameters comprises current value of the respective coefficients, denoted C(n) in FIG. 19, differential value of the coefficients, denoted D(n) and, goal value of the coefficients, denoted T(n).

In FIG. 19,

406 to 408 are provided to respectively store current value C(n), differential value D(n) and goal value T(n), of each filter coefficient. For interpolation, a

401 compares a current value C(n) with a goal value T(n) for each filter coefficient. The comparison result from the

401 is supplied to an

404 and

403. The

404 inverts the differential value D(n) when T(n)<C(n). The

403 determines whether the current value C(n) has reached the goal T(n). An

405 adds the current value C(n) and the output from the

404 indicative of a selectively inverted differential value to change (update) the current value C(n) by the difference D(n). For T(n)≧C(n), the

405 outputs an updated current value of C(n)+D(n) while for T(n)<C(n), it outputs C(n)-D(n). A

402 compares the updated current value from the

405 with the goal value. The comparison result from the

402 is input to the

403. The

403 detects when the current value C(n) has reached the goal T(n) i.e., completion of interpolation. This is indicated by either T(n)≧C(n) and T(n)< adder output, or T(n)<C(n) and T(n)≧ adder output. The

403 output controls SW1

409 to select a new current value from the

405 output and the goal value T(n). If the goal has been reached, the

409 selects the goal value T(n). Otherwise, it selects the

405 output.

In accordance with the invention, there is provided a

410 which selects either the current value from

406 or a new current value from the

409 under the control of a control signal F. The control signal F is externally supplied from

302. It takes the form of a binary signal. Logic "0" level of the control signal F enables the

301 to perform the interpolation which comprises updating the

406 by writing a new current value from the

409 through the

410. Logic "1" level of the control signal F, however, inhibits the

301 from performing the interpolation; the current value read out from the

406 is directly fed back to the

406 without any change.

During a logic "0" period of the control signal,

302 supplies a new set of parameters i.e., new goal values T(n) and new differential values D(n) to externally update the contents of the

408 and 407.

This arrangement makes it possible to synchronize interpolating operations among the plurality of filter coefficients. Specifically, control signal F is switched to logic "0" level after all parameters in the

407 and 408 have been updated by the new set of parameters from

302 during logic "1" level period of control signal F during which the

301 is inhibited. At the next sampling cycle following this switching, the

301 restarts its interpolating operations using the goal and

407 and 408 having parameters all updated. This is the simultaneous restart of multicoefficient interpolations by the

301 which operates on a time divisional multiplexing basis. Therefore, the

300, which uses the interpolated coefficients from the interpolator to filter an input signal, is accurately controlled as intended by

302. The simultaneous or synchronizing function is most effective for digital signal processing using a plurality of filter coefficients and having a high sensitivity to timing errors or sampling skews in the plurality of coefficients.

Though not shown in FIG. 19,

302 sets the

406 to initial values of current coefficients at a filter initializing time as well as initializing the difference and

407 and 408.

FIG. 21 shows a more specific arrangement of the

301. Various components of the

301 are controlled by timing signals from a timing generator or

17 to achieve a time division multiplexing function. A

1 stores goal, difference and current values of a plurality of filter coefficients and corresponds to the combination of

406 to 408 in FIG. 19.

302 supplies the interpolator with data and signals ED, EDCK, EA, EACK and F, shown at left-hand of FIG. 21. Among them, F is a single-bit binary control signal and entered into the

17. Logic "1" level of the control signal F causes the

17 to inhibit the

301 from performing interpolation, and at the same time, permits

302 to update the

1 using ED, EDCK, EA, and EACK. A new parameter is carried by ED bus and loaded into

7 by EDCK clock applied thereto. The EDCK clock is also supplied to the

17. Address information on the new parameter is carried by EA bus and loaded into

8 by EACK clock applied thereto. EACK clock is also applied to the

17.

7 output, indicative of a new parameter, is supplied to the data input to the

1 via a

14 which is controlled by a selecting signal SL3 from the

17.

8 output, indicative of a new parameter address, is supplied to the address input to the

1 via a

15 which is also controlled by the same selecting signal SL3. Therefore, a new parameter, which has been sent from

302, is written into the

1 at the designated address when the

1 receives a write signal WR from the

17. Note that this writing is enabled during a logic "1" level period of the control signal F. The

14 has a second input for receiving an interpolated (updated) coefficient obtained in the

301. The

15 has a second input for receiving address information from the

17.

FIG. 22 illustrates parameter allocation of the

1. According to the illustrated allocation, a group of parameters T, D, C for each filter coefficient are placed at three successive addresses. Specifically, the first three successive addresses store parameters T(0), D(0) and C(0) for the first coefficient, the second three addresses store T(1), D(1) and C(1) for the second coefficient, and so on, and the last three addresses store T(N-1), D(N-1), and C(N-1) for N-th coefficient. These N coefficients may be used in the

300 to process a single signal or channel. If the

300 is a multichannel digital filter which processes M signal channels on a time division multiplexing according to the same algorithm, it will use N/M coefficients per each signal channel and requires 3N/M parameters on the part of the

1. In some application, the number of filter coefficients may be different from one signal channel to another. For a single channel digital filter of second order IIR type in FIG. 20, T(0), D(0) and C(0) may define a parameter set for b1 coefficient, T(1), D(1) and C(1) for b2 coefficient and T(2), D(2) and C(2) for K coefficient. The parameter storage allocation in FIG. 22 is merely an example. Any other storage allocation addressable by the

17 may be employed.

Turning back to FIG. 21, TR, CR, DR and

3 to 5 are provided to temporarily store a parameter output from the

1. Specifically,

2 is for storing a coefficient goal value T(n),

3 for a current value C(n),

4 for a differential value D(n) and OR register 5 for supplying a coefficient current value to the

300.

2 to 5 are controlled by clocks CK1 to CK4, respectively, from the

17. A

12, which is controlled by a selecting signal SL1 from the

17, selects either a goal value output T(n) from

2 or a differential value output D(n) from DR register C to provide a first input to an adder/

16. Another

13, which is controlled by a selecting signal SL2 from the

17, selects either a current value output from

3 or an output from

6 to provide a second input to the adder/

16.

6 is controlled by clock CK5 from the

17 to provide the adder/

16 output.

FIG. 23 indicates how the adder/

16 is controlled by the combination of a three-bit control signal CAL from the

17, and the state of

9 which fetches a sign bit S of the adder/

16 output at CK5 clock time. With CAL=000, the adder/

16 simply passes its first input (denoted SL1 in FIG. 23) from the

12 to

6. With CAL=001, the adder/

16 sums its

1 and its second input, denoted

2, from the

13 and pass the sum (SL1+SL2) to AR register. With CAL=010, the adder/

16 subtracts SL1 from SL2 and passes the result (SL1-SL2) to

6. With CAL=100 and F1=1, the adder/

16 executes (SL2-SL1). With CAL=100 and F1=0, it executes (SL2+SL1).

Turning back to FIG. 21,

9 output is fetched by

10 at the next CK5 clock time.

9 output and

10 output are exclusively ORed by

11 to develop a signal FE. The signal FE is supplied to the

17.

9 state indicates magnitude comparison between goal T(n) and current value C(n) at one time. At another time after this information is copied into

10,

9 state indicates magnitude comparison between goal T(n) and updated current value given by C(n)±D(n) where the sign is determined by the magnitude comparison between T(n) and C(n). The signal FE corresponds to the

409 output in FIG. 19. From the signal FE, the

17 determines whether the current value has reached the goal or not. Specifically, FE=0 (i.e., F1=F2=1 or F1=F2=0) indicates that a new current value from the adder/

16 has not yet reached the goal, namely, the interpolating process is going on. FE=1 signals that the goal has been reached, which thus, indicates completion of the interpolating process. With FE=0 (during interpolating period), to update the current value in the

1 the

301 writes into the

1 the interpolated coefficient C(n)±D(n) from the adder/

16 by way of

6 and

14 under the control of the

17. With FE=1 indicative of completion of interpolation process, the

301 writes into the memory 1 a goal value from

2 by way of

6 and the

14, as a current value in the

1.

FIG. 24 is a flow chart of the operation of the interpolator in FIG. 21. For each pass of the flow, the interpolator generates an operative filter coefficient of the digital filter. Since the interpolator must supply the digital filter 300 a plurality of operative filter coefficients as many as needed in the digital filter, the interpolator repeats the operation of FIG. 24 as many times as the number of operative filter coefficients during each sampling cycle of the digital filter while shifting the addressing of the

1, thus achieving a time division multiplexing.

In the first step 7-4 with a cycle of generating n-th operative coefficient, timing generator or

17 reads, from the

1, goal T(n) of the n-th coefficient and sets

2 to T(n).

In the next step 7-2, the

1 outputs a current value of the n-th coefficient and loads it into

3 and OR register 5 for providing an operative filter coefficient to the

300. In the step 7-3, the

17 causes the

12 to select the goal value T(n) from

2, causes the

13 to select the current value T(n) from

3, supplies CAL=010 to the adder/

16 to execute (TR-CR) or (T(n)-C(n)), the sign bit S of which is then set into

9, and reads a differential value D(n) of the n-th coefficient from the

1 to load it into

4.

As a result, at step 7-4,

9 supplies the adder/

16 the sign bit F1 indicative of the magnitude comparison between the goal T(n) and the current value C(n). At this time, the

16 applies CAL=100 to the adder/

16. Thus, if F1=1, i.e., goal T(n)<current value C(n), the adder/

16 executes C(n)-D(n) as shown in block 7-5, while if F1=0, i.e., T(n)≧C(n), it executes C(n)+D(n), as shown in block 7-6. The adder/

16 output is then loaded into

6 under the control of the

17.

In step 7-7, the

17 causes the

12 to select the goal T(n) from

2, causes the

13 to select the updated current value C(n)±D(n) from

6, and supplies CAL=010 to the adder/

16 to execute (goal value T(n)-the updated current value). Further, the

17 moves the state of

9, indicative of the magnitude comparison between the goal T(n) and the (old) current value C(n), to

10, and sets

9 to the sign bit S from the adder/

16, indicative of the magnitude comparison between the goal T(n) and the new or updated current value C(n)±D(n).

The following process depends on the control signal F supplied from external CPU 302 (7-8). If F=1, the

17 executes new parameter writing into the memory 1 (7-10) assuming that a new parameter has been supplied from

302. Strictly, the writing should be executed when EDR and

7 and 8 have been loaded with correct information i.e., a new parameter and a corresponding address. To assure this, strobe signals EDCK and EACK which are sent from

302 to load EDR and

7 and 8 with data on ED bus and on EA bus, respectively, are also supplied to the

17. Then, the

17 causes the

14 to select

7 i.e., new parameter, causes the

15 to select

8 output, and applies a write signal WR to the

1 to execute the new parameter writing.

As seen in FIG. 24, operations following the new parameter writing (parameter updating) 7-10 do not include any process that feeds back to the

1 with a new sample of current coefficient created by the adder/

16. In this way, the

301 is inhibited from performing the interpolation while an external write mode is established by F=0. Each current value C(n) in the

1 is fixed and supplied, as the fixed operative coefficient, to the

300 by

5. Therefore, once setting F to "0"

302 can freely supply a new set of parameters, one at a time through ED, EA, EDCK and EACK to update the

1 with the new set, as indicated in the time chart of FIG. 25.

In FIG. 25, the second order IIR filter shown in FIG. 20 is assumed for the

300. At the filter initializing time,

302 sends the

301 the following parameters: goal, current and differential values, KT, KC and KD for K coefficient; goal, current and differential values, b1T, b1C and b1D for b1 coefficient; and goal, current and differential values b2T, b2C and b2D for b2 coefficient. For the following updating times, current parameters KC, b1C, b2C are not sent to avoid skipping of operative filter coefficients of the digital filter.

As indicated in FIG. 25,

302 switches F to "0" after having sent a new parameter set. Within the

301, the transition of the control signal F will be made effective from the beginning of the next sampling cycle in which the

301 produces a set of operative coefficients for the

302. To this end, the

17 includes a delayed (synchronizing) flip flop (not shown) with a data input for receiving the control signal F directly supplied from

302. The flip flop is controlled by a synchronizing signal generated in synchronism with the sampling cycle. Thus, if the control input F is changed to "0", this will change the flip flop state at the next occurrence of the synchronizing signal. The delayed and synchronized control signal F from the flip flop is used by the

17 in step 7-8 in FIG. 22 as a conditional branching signal.

In this way, if

302 changes the control signal F to logic "0" level at some time in a sampling cycle, the

301 will detect F=0 at step 7-8 in the next sampling cycle. During a period of F=0, the

17 operates differently depending on the signal FE from the

11. If FE=0 (F1=F2), the updated current value C(n)±D(n) has not yet reached the goal value T(n). Thus, the

17 writes the updated (newly interpolated) current value into the

1 from

6 through the selector 14 (7-12). On the other hand, if FE=1 (F1 is unequal to F2), the goal has been reached so that the

17 supplies CAL=000 to the adder/

16 to move the goal value T(n) from TR register 2 to

6, and then moves the goal value T(n) from

6 to the

1 at the address of the current value (7-11, 7-12).

In this manner, from the sampling cycle immediately after the transition of the control signal F into logic "0" level, the

17 restarts interpolating operations on the plurality of coefficients C(0), C(1), C(2) and so on using parameters all updated by

302.

FIG. 26 shows how the coefficient interpolation proceeds in the

301. As indicated by SY, the interpolation starts from the sampling cycle next to the switching of the control signal F into logic "0" level. Within this sampling cycle, the

301 produces a first set of interpolated coefficient samples one at a time. This assures synchronous interpolations performed by a time-division-multiplexing based system i.e., the interpolator. The synchronous function of the

301 allows

302 to control the

300 with high accuracy and on a real-time basis.

Though not shown in FIG. 27, various control signals are supplied to various parts of the processing circuit. The

17 in FIG. 21 may provide such control signals.

At step 11-1 in FIG. 28, the processing circuit, which is pipeline structured, reads from

21, a preceding sample w1 of i-th output signal (where i=0 to 2) and loads it into

24 via

28. At this time, the

301 in FIG. 21 produces a coefficient b1 and loads it into OR

5. In addition, at step 11-1, the processing circuit performs a partial processing of (i-1)mod3-th signal according to the nature of pipelining. Specifically, the processing circuit causes a

22 to multiply a sample of the (i-1)mod3-th input signal IN and a sample of K coefficient from OR register 5 (FIG. 21), and loads the result (K×IN) into

25. Further, the processing circuit causes an

23 to add a sample of b2w2 from

25 and a sample of b1w1 from ACC register (accumulator) 26 via

29, and reloads the result (b1w1+b2w2) into

26.

At the next step 11-2, the processing circuit causes the

22 to multiply the previous sample w1 of the i-th output signal from

24 and b1 coefficient from

5, and loads the result (b1×w1) into

25. At the same time, the

301 loads a current sample of b2 coefficient into

5. Further, the processing circuit loads a second preceding sample w2 of the i-th output signal OUT into WR register 24 from

21. For the (i-1)mod3-th signal, the processing circuit causes the

23 to add K×IN from

25 and (b1×w1+b2×w2) from

26, loads into

26 the result indicative of a new sample of the (i-1)mod3-th output signal.

At step 11-3, the processing circuit causes the

22 to multiply the second preceding sample w2 of the i-th output signal OUT from

25 and b2 coefficient from

5, and loads the result (b2×w2) into

25, loads a current sample IN of the i-th input signal into

24 via the

28. At the same time, the

301 loads a current sample of K coefficient into OR register. The precessing circuit moves b1w1 from MR register to ACC register 26 via the

23 which now receives "0" from the

29. For the (i-1)mod3-th signal, the processing circuit moves the new sample of the (i-1)mod3-th output signal from

26 to OO register 27 for actually providing the output signal sample, and writes into WRAM 21 a sample of (i-1)mod3-th output signal from

27.

After the step 11-3, the processing circuit processing while changing addressing to

21.

In FIG. 20, a

46 receives a sample of output signal OUT and introduces a delay of one sampling cycle to provide a first preceding sample w1 of the output signal. A

47 coupled to the

46 introduce an additional delay of one sampling time to provide a second preceding sample w2 of the output signal. A

42 multiplies the first preceding sample w1 by b1 coefficient. Another

43 multiplies the second preceding sample w2 by b2 coefficient. An

45 adds b1w1 from the

42 and b2w2 from the

43. A

41 multiplies a sample of the input signal IN by K coefficient. An

44 adds KI from the

41 and (b1w1+b2w2) from the

45 to produce a sample of the output signal.

In summary, the digital filter system of the second embodiment employs

302 that supplies the

301 the control signal F. With F=1,

302 can freely send the interpolator 301 a new set of parameters. In the meantime, the

301 is inhibited from performing the interpolations while allowing the

1 to be updated to the new parameter set from

302. In response to the transition of the control signal F from "1" to "0", the

301 restarts the synchronized interpolations of a plurality of operative filter coefficients using the updated parameters. The interpolated samples of the operative filter coefficients are used in the

300 for processing or filtering a digital signal such as digital tone signal. Therefore,

302, in cooperation with the

301, can dynamically control the

300 with high accuracy and on a real-time basis. The operating filter coefficients that determine the operating point of the

300 are controlled with a smooth change and in synchronism with one another.

FIG. 29 shows a basic arrangement of a modified digital filter system. FIG. 30 shows the operation thereof. This system employs two memory banks A and B for parameter storage. These two banks A and B are alternately referenced by

100M under the control of a control signal F supplied from

200M.

If the control signal F is at a first level, e.g., logic "0" level, selectors S1 and S2 are each placed at a position indicated by a solid line. Accordingly a set of new parameters comprising new goals and differential values are supplied to bank B from

200M via selector S1. Meanwhile, the

100M reads parameters from bank A via the selector S2 to interpolate or update a current value C(n) of each filter coefficient in

500, which is then supplied to

300M.

When the control signal F is changed to logic level "1", this causes the selectors S1 and S2 to move to a position indicated by a dot line. A new parameter set from

200M are now written into bank A via the selector S1. Bank B, which now serves as an active parameter memory, supplies stored parameters to the

100M via selector S2 for interpolation of the current values in the memory 500 (see FIG. 30).

At an initial time,

200M initializes the

500 in the same manner as the second embodiment. Thereafter, the digital filter system operates as described above.

The digital filter system in FIG. 29 requires an increased storage capacity, two times that of the second embodiment, for storing goal and differential parameters. The system, however, has the advantage that the

100M can run continously; no inhibited period is needed for updating the parameters. Since

200M can predict from the goal and differential values, and the operation speed of the interpolator, when the operative filter coefficients reach the goal, it can send new parameters at an appropriate time after changing the control signal F level. In doing so, when a goal has been reached, the interpolator will restart interpolating of coefficients toward the new goal without any substantial delay, thus providing more continous control of the digital filter.

In the second embodiment, exact synchronism is accomplished among interpolating operations on a plurality of filter coefficients by providing the synchronizing means within the

17 which synchronizes the external control signal F from

302 with its internal sampling cycle. Such synchronizing means may be omitted, however, except for applications with most severe requirements of digital signal processing, because such omission will only introduce at most one sampling time error among the coefficients.