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US5519351A - Method for arranging tree-type clock signal distributing circuit with small clock skew - Google Patents

️Tue May 21 1996

Method for arranging tree-type clock signal distributing circuit with small clock skew Download PDF

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Publication number

US5519351A

US5519351A US08/338,774 US33877494A US5519351A US 5519351 A US5519351 A US 5519351A US 33877494 A US33877494 A US 33877494A US 5519351 A US5519351 A US 5519351A Authority

United States

Prior art keywords

functional blocks

segments

classes

clock

processing unit

Prior art date

1993-11-10

Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired - Fee Related

Application number

US08/338,774

Inventor

Hiroshi Matsumoto

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NEC Electronics Corp

Original Assignee

NEC Corp

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1993-11-10

Filing date

1994-11-10

Publication date

1996-05-21

1994-11-10 Application filed by NEC Corp filed Critical NEC Corp

1994-11-10 Assigned to NEC CORPORATION reassignment NEC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MATSUMOTO, HIROSHI

1996-05-21 Application granted granted Critical

1996-05-21 Publication of US5519351A publication Critical patent/US5519351A/en

2003-02-25 Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC CORPORATION

2014-11-10 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

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Classifications

- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/396—Clock trees
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages

Definitions

the present invention relates to a method for arranging a tree-type clock signal distributing circuit in a synchronous integrated circuit.
a main wide connection having a small resistance is arranged at a center of the integrated circuit, and a number of side branch connections are arranged between the main wide connection and the functional blocks, thus realizing a fish back bone shaped configuration for a clock signal distributing circuit.
the side branch connections are actually slim. Therefore, in order to sufficiently suppress the fluctuation of delay of the clock signal to the functional blocks, the main wide connection should be made as wide as possible, thereby increasing the chip area.
the first prior art method does not contribute to the integration and the high frequency of the clock signal.
a second prior art method for arranging a clock signal distributing circuit in a synchronous integrated circuit uses a geometrical tree synthesis method, i.e., a geometrical tree-type clock signal distributing circuit where clock buffers are determined from an upstream side of the clock signal to a downstream side thereof (see JP-A-HEI2-62675, JP-A-HEI2-93917 and JP-A-HEI2-134919). This will be explained later in detail.
the functional blocks are not always arranged in regular positions, the functional blocks are not always arranged near clock buffers, thereby increasing the clock skew. Also, if the functional blocks are forcibly adapted to the clock buffers, logic gate combination circuits connected to the functional blocks are not suitably arranged. Further, when the distribution of the functional blocks is not homogeneous, the result is a lot of unused clock buffers and a lot of clock buffers having a small number of fan-outs, such as a single fan-out, thereby increasing the chip area, thus reducing the integration.
a third prior art method for arranging a clock signal distributing circuit in a synchronous integrated circuit uses a logical tree synthesis method, i.e., a logical tree-type clock signal distributing circuit where clock buffers are determined from a downstream side of the clock signal to an upstream side thereof (see T. Kimoto et al., "OpenCAD Clock Tree Synthesis", NEC Technical Bulletin, Vol. 45, No. 8, pp. 16-20, 1992). That is, the functional blocks are divided into classes each having the same number of functional blocks which are located in the same neighborhood. Then, one clock buffer is arranged at a substantial center position of each of the classes, and the clock buffer is connected to the functional blocks thereof.
the plurality of functional blocks are divided into a plurality of segments.
Each of the segments is further divided into classes whose number is dependent upon the density of the functional blocks within each of the segments.
a distribution of the functional blocks allocated to one class is homogeneous within the segment to which the class belongs, and one clock buffer is allocated at a substantial center position of the functional blocks within the class.
FIG. 1 is a diagram illustrating a prior art geometrical tree-type clock signal distributing circuit
FIG. 2 is a diagram illustrating a prior art logical tree-type clock signal distributing circuit
FIGS. 3A-3C are diagrams of an actual example of the clock signal distributing circuit of FIG. 2;
FIG. 4 is a block circuit illustrating an apparatus for carrying out an embodiment of the method for arranging a tree-type clock signal distributing circuit according to the present invention
FIG. 5 is a block diagram illustrating a combination of FIGS. 5A and 5B;
FIGS. 5A and 5B are flowcharts showing the operation of the control circuit of FIG. 4;
FIG. 6 is a diagram illustrating example of the segments used in the routine of FIG. 5;
FIG. 7 is a detailed flowchart of the quantization step of FIG. 5;
FIG. 8 is a detailed flowchart of the functional block allocating step of FIG. 5;
FIG. 9 is a graph showing the operation of the routine of FIG. 8.
FIGS. 10A-10C are diagrams showing an actual example of the clock signal distributing circuit obtained by the routine of FIG. 5.
FIGS. 1, 2 and 3A-3C Before the description of the preferred embodiment, a prior art method for arranging a tree-type clock signal distributing circuit will be explained with reference to FIGS. 1, 2 and 3A-3C.
FIG. 1 which illustrates a tree-type clock signal distributing circuit for explaining a geometrical tree synthesis method
clock buffers are arranged from an upstream side of a clock signal to a downstream side thereof (see JP-A-HEI2-62675, JP-A-HEI2-93917 and JP-A-HEI2-134919).
the fan-out of each clock buffer is 2, to simplify the description. That is, a clock signal CLK is fed via a horizontal connection C 1 , to an input of a 1st level clock buffer 1.
the clock buffer 1 has two outputs, i.e., two vertical connections C 2-1 and C 2-2 which are connected to 2nd level clock buffers 2-1 and 2-2, respectively.
each of the clock buffers 2-1 and 2-2 has two outputs, i.e., two horizontal connections, such as C 3-1 and C 3-2 , which are connected to 3nd level clock buffers 3-1 and 3-2, respectively.
the length of each of the connections C 3-1 and C 3-2 to the connections C 2-1 and C 2-2 is definite. This method is repeated to obtain a five-storied hierarchic fractal-like configuration which is geometrically fixed.
each of the final level clock buffers 5-1 through 5-16 is connected to a number of functional blocks such as two flip-flops (not shown) located in the neighborhood thereof.
the flip-flops are not always arranged in regular positions, the flip-flops are not always arranged near the final level clock buffers 5-1 through 5-16, thereby increasing the clock skew. Also, if the flip-flops are forcibly adapted to the final level clock buffers 5-1 through 5-16, logic gate combination circuits connected to the flip-flops are not suitably arranged. Also, when the distribution of the flip-flops is not homogeneous, the result is a lot of unused final level clock buffers and a lot of final level clock buffers having a small number of fan-outs such as a single fan-out, thereby increasing the chip area, thus reducing the integration.
FIG. 2 which illustrates a tree-type clock signal distributing circuit for explaining a logical tree synthesis method
clock buffers are arranged from a downstream side of a clock signal to an upstream side thereof (see T. Kimoto et al., "OpenCAD clock Tree Synthesis", NEC Technical Bulletin, Vol. 45 No. 8, pp. 16-20, 1992). That is, flip-flops are divided into classes. For example, flip-flops 111 to 113 are allocated to a class K1; flip-flops 121 to 123 are allocated to a class K2; and flip-flops 131 to 133 are allocated to a class K3. In this case, the flip-flops allocated to each class are in the neighborhood of each other.
the number of flip-flops allocated to each class is the same, in this case, 3.
one final level clock buffer such as 11 is arranged at a substantial center position of each of the classes, and this clock buffer is connected by connections such as C 111 , C 112 and C 113 to the flip-flops 111, 112 and 113.
the above-mentioned steps are repeated to obtain a two-storied hierachic configuration which is, however, not geometrically fixed.
fan-outs of each clock buffer can be balanced to suppress the increase of the clock skew.
FIG. 4 which illustrates an apparatus 40 for carrying out an embodiment of the method for arranging a tree-type clock signal distributing circuit according to the present invention
the apparatus 40 is constructed by a computer which includes an input/output (I/O) interface 401, a central processing unit (CPU) 402, a read-only memory (ROM) 403 for storing programs and fixed data, a random access memory (RAM) 404 for storing temporary data, and the like.
the I/O interface 401 receives various input signals from the keyboard 41 and the like, and generates various signals and transmits them to a display such as a liquid crystal display (LCD) 42 and the like.
LCD liquid crystal display
the present invention is applied to a 200 K gate standard cell base integrated circuit, as an example. Also, an area which requires no clock signal distributing line is omitted from the integrated circuit in advance.
step 501 the number N of stages of a clock tree, the number Mi of fan-outs of an i-th stage and the number R 0 of dummy flip-flops are determined by
step 502 the R 0 dummy flip-flops are inserted into adequate positions of the integrated circuit.
i a first stage of the clock tree on the downstream side thereof is indicated.
step 504 an average density .sub. ⁇ o of flip-flops within the integrated circuit is calculated.
the integrated circuit is divided into a number of square segments each having a length L which is a multiple of a grid length and is closest to n ⁇ M i /.sub. ⁇ o as shown in FIG. 6.
L which is a multiple of a grid length and is closest to n ⁇ M i /.sub. ⁇ o as shown in FIG. 6.
each segment includes M 1 ⁇ n 2 flip-flops.
n 2 clock buffers are allocated to each segment.
the density of flip-flops is not homogeneous.
a density .sub. ⁇ of flip-flops within each of the segments is calculated.
the segments having the density of 0 are omitted.
a minimum value .sub. ⁇ min of the densities .sub. ⁇ is selected.
step 509 it is determined whether or not
step 511 which increases the multiplication constant n by +1, and then, the control at steps 506 through 509 is repeated.
the number p of classes of each segment is quantized in accordance with the minimum value .sub. ⁇ min of the densities .sub. ⁇ . This will be explained later in detail with reference to FIG. 7.
step 512 the number of flip-flops allocated to each of the classes is determined. This will be also explained with reference to FIG. 8.
flip-flops are allocated to the classes within each of the segments.
a distribution of the flip-flops allocated to each class is homogeneous within the segment to which this class belongs.
the flip-flops within each of the segments are randomly selected and allocated sequentially to the classes thereof.
one clock buffer is allocated to each of the classes.
one clock buffer is inserted at a substantial center position, i.e., an arithmetic average position of the flip-flops of each of the classes, and is connected by connections to the flip-flops.
step 515 the value i is incremented by +1, and at step 516, it is determined whether or not i>N is satisfied. Only when i>N, does the control proceed to step 518. Otherwise, the control proceeds the step 517 which replaces the flip-flops with the clock buffers allocated at step 514, and then return to step 504, thus repeating the above-mentioned steps 504 through 514. In other words, the control at steps 504 through 514 is repeated until the number of allocated clock buffers is one.
a final clock buffer which is finally arranged at a substantial center position of all of the flip-flops is connected by a connection to a clock driver (not shown) which receives an external clock signal or an internal clock signal derived from a control circuit (not shown).
the input node number .sub. ⁇ N represents a number of flip-flops.
step 703 a density of flip-flops for a segment S is calculated by
a S is an area of the segment S; and N S is the number of flip-flops within the segment S.
step 604 a value .sub. ⁇ S /.sub. ⁇ min is calculated, and it is determined whether the value .sub. ⁇ S /.sub. ⁇ min is an integer. Only when the value .sub. ⁇ S /.sub. ⁇ min in an integer, does the control proceed to step 705 which causes the number p of classes to be .sub. ⁇ S /.sub. ⁇ min. Otherwise, the control proceeds to step 706.
an integer p L closest to the value .sub. ⁇ S /.sub. ⁇ min but smaller is calculated, i.e.,
step 706 an integer p H closest to the value .sub. ⁇ S .sub. ⁇ min but larger is calculated, i.e.,
a value .sub. ⁇ S ⁇ .sub. ⁇ o is compared with the input node number .sub. ⁇ N.
step 708 a value .sub. ⁇ S ⁇ .sub. ⁇ o ⁇ .sub. ⁇ N
the control proceeds to step 709 which causes the number p of classes to be p L .
step 710 causes the number p of classes to be p H .
step 711 causes the number p of classes to be p H .
a value .sub. ⁇ S /.sub. ⁇ min -p L is compared with a value p H -.sub. ⁇ S /.sub. ⁇ min.
the number p of classes is caused to be p L or p H .
the selection of p L and p H is carried out alternately or randomly.
step 705, 709, 710 and 712 proceeds to step 713 which increments the segment area variable .sub. ⁇ A and the input node number .sub. ⁇ N by
a value S max represents the number of segments.
step 716 the routine of FIG. 7 returns to step 512 of FIG. 5.
the number p of classes within each of the segments is quantized so that the value .sub. ⁇ S /.sub. ⁇ N is brought close to the average density .sub. ⁇ o.
step 801 the segment number S is initialized, i.e.,
a number N S ,i of flip-flops allocated to a class i of the segment S is calculated.
the number N S ,i is determined so that the following value:
each value .sub. ⁇ S, i is a multiple of M i .
control at step 802 is repeated by steps 803 and 804 for all of the segments.
the flip-flops (clock buffers) belonging to each of the classes are arranged homogeneously within one segment to which this class belongs.
the density of flip-flops (clock buffers) allocated to each class is close to the minimum value .sub. ⁇ min.
the length of connections C1 between a clock buffer B1 (B2, B3) and flip-flops FF1 (FF2, FF3) in a region 10B where the density of flip-flops FF is relatively large is about the same as that of connections C2 between clock buffers B and flip-flops FF in a region 10c were the density of flip-flops FF is relatively small.
all of the connections for clock signal to the flip-flops do not fluctuate, i.e., are homogeneous.
the clock skew can be reduced.

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Abstract

In a synchronous integrated circuit including a plurality of functional blocks, the plurality of functional blocks are divided into a plurality of segments. Each of the segments is further divided into classes whose number is dependent upon the density of the functional blocks within each of the segments. A distribution of the functional blocks allocated to one class is homogeneous within the segment to which the class belongs, and one clock buffer is allocated at a substantial center position of the functional blocks within the class.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for arranging a tree-type clock signal distributing circuit in a synchronous integrated circuit.

2. Description of the Related Art

Recently, as the speed of integrated circuits has been increased, a timing margin between functional blocks such as flip-flops within the integrated circuits has become critical. In order to avoid a critical condition regarding a time margin, a clock signal is introduced into an integrated circuit, so that all of the functional blocks can be almost simultaneously operated, thus realizing a so-called synchronous integrated circuit.

Even in such a synchronous integrated circuit, when the integration is very advanced, the structure becomes very fine, and the chip area is enlarged, so the resistance of connections for transmitting the clock signal and the capacitance of input nodes of the functional blocks for the clock signal have been both increased. As a result, the delay of the clock signal to the functional blocks fluctuates in accordance with the length of the connection and the number of fan-outs, to thereby increase the clock skew. This is an obstacle in increasing of the frequency of the clock signal.

In the prior art, the fluctuation of delay due to the length of the connections for the clock signal has been compensated for by making the connection configuration for the clock signal a special geometrical or logical configuration.

According to a first prior art method for arranging a clock signal distributing circuit in a synchronous integrated circuit, a main wide connection having a small resistance is arranged at a center of the integrated circuit, and a number of side branch connections are arranged between the main wide connection and the functional blocks, thus realizing a fish back bone shaped configuration for a clock signal distributing circuit. In the fist prior art method, however, the side branch connections are actually slim. Therefore, in order to sufficiently suppress the fluctuation of delay of the clock signal to the functional blocks, the main wide connection should be made as wide as possible, thereby increasing the chip area. Thus, the first prior art method does not contribute to the integration and the high frequency of the clock signal.

A second prior art method for arranging a clock signal distributing circuit in a synchronous integrated circuit uses a geometrical tree synthesis method, i.e., a geometrical tree-type clock signal distributing circuit where clock buffers are determined from an upstream side of the clock signal to a downstream side thereof (see JP-A-HEI2-62675, JP-A-HEI2-93917 and JP-A-HEI2-134919). This will be explained later in detail.

In the second prior art method, however, since the functional blocks are not always arranged in regular positions, the functional blocks are not always arranged near clock buffers, thereby increasing the clock skew. Also, if the functional blocks are forcibly adapted to the clock buffers, logic gate combination circuits connected to the functional blocks are not suitably arranged. Further, when the distribution of the functional blocks is not homogeneous, the result is a lot of unused clock buffers and a lot of clock buffers having a small number of fan-outs, such as a single fan-out, thereby increasing the chip area, thus reducing the integration.

A third prior art method for arranging a clock signal distributing circuit in a synchronous integrated circuit uses a logical tree synthesis method, i.e., a logical tree-type clock signal distributing circuit where clock buffers are determined from a downstream side of the clock signal to an upstream side thereof (see T. Kimoto et al., "OpenCAD Clock Tree Synthesis", NEC Technical Bulletin, Vol. 45, No. 8, pp. 16-20, 1992). That is, the functional blocks are divided into classes each having the same number of functional blocks which are located in the same neighborhood. Then, one clock buffer is arranged at a substantial center position of each of the classes, and the clock buffer is connected to the functional blocks thereof. Thereafter, the above-mentioned steps are repeated by replacing the functional blocks with the clock buffers, until the number of the clock buffers is reduced to one. Thus, the fan-outs of each clock buffer can be balanced to suppress the increase of the clock skew. This will be explained later in detail.

In the third prior art method, however, if the density of functional blocks is not homogeneous within the integrated circuit, the length of connections to the clock buffers fluctuates, so that the clock skew is increased.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method for arranging a tree-type clock signal distributing circuit in a synchronous integrated circuit which can reduce the clock skew due to the fluctuation of length of connections even when the density of functional blocks is not homogeneous.

According to the present invention, in a synchronous integrated circuit including a plurality of functional blocks, the plurality of functional blocks are divided into a plurality of segments. Each of the segments is further divided into classes whose number is dependent upon the density of the functional blocks within each of the segments. A distribution of the functional blocks allocated to one class is homogeneous within the segment to which the class belongs, and one clock buffer is allocated at a substantial center position of the functional blocks within the class.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from the description as set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:

FIG. 1 is a diagram illustrating a prior art geometrical tree-type clock signal distributing circuit;

FIG. 2 is a diagram illustrating a prior art logical tree-type clock signal distributing circuit;

FIGS. 3A-3C are diagrams of an actual example of the clock signal distributing circuit of FIG. 2;

FIG. 4 is a block circuit illustrating an apparatus for carrying out an embodiment of the method for arranging a tree-type clock signal distributing circuit according to the present invention;

FIG. 5 is a block diagram illustrating a combination of FIGS. 5A and 5B;

FIGS. 5A and 5B are flowcharts showing the operation of the control circuit of FIG. 4;

FIG. 6 is a diagram illustrating example of the segments used in the routine of FIG. 5;

FIG. 7 is a detailed flowchart of the quantization step of FIG. 5;

FIG. 8 is a detailed flowchart of the functional block allocating step of FIG. 5;

FIG. 9 is a graph showing the operation of the routine of FIG. 8; and

FIGS. 10A-10C are diagrams showing an actual example of the clock signal distributing circuit obtained by the routine of FIG. 5.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before the description of the preferred embodiment, a prior art method for arranging a tree-type clock signal distributing circuit will be explained with reference to FIGS. 1, 2 and 3A-3C.

In FIG. 1, which illustrates a tree-type clock signal distributing circuit for explaining a geometrical tree synthesis method, clock buffers are arranged from an upstream side of a clock signal to a downstream side thereof (see JP-A-HEI2-62675, JP-A-HEI2-93917 and JP-A-HEI2-134919). In FIG. 1, the fan-out of each clock buffer is 2, to simplify the description. That is, a clock signal CLK is fed via a horizontal connection C₁, to an input of a 1st

level clock buffer

1. The

clock buffer

1 has two outputs, i.e., two vertical connections C_2-1 and C_2-2 which are connected to 2nd level clock buffers 2-1 and 2-2, respectively. In this case, the length of each of the connections C_2-1 and C_2-2 to the connection C₁ is definite. Similarly, each of the clock buffers 2-1 and 2-2 has two outputs, i.e., two horizontal connections, such as C_3-1 and C_3-2, which are connected to 3nd level clock buffers 3-1 and 3-2, respectively. In this case, the length of each of the connections C_3-1 and C_3-2 to the connections C_2-1 and C_2-2 is definite. This method is repeated to obtain a five-storied hierarchic fractal-like configuration which is geometrically fixed. Then, each of the final level clock buffers 5-1 through 5-16 is connected to a number of functional blocks such as two flip-flops (not shown) located in the neighborhood thereof.

In FIG. 1, however, as stated above, since the flip-flops are not always arranged in regular positions, the flip-flops are not always arranged near the final level clock buffers 5-1 through 5-16, thereby increasing the clock skew. Also, if the flip-flops are forcibly adapted to the final level clock buffers 5-1 through 5-16, logic gate combination circuits connected to the flip-flops are not suitably arranged. Also, when the distribution of the flip-flops is not homogeneous, the result is a lot of unused final level clock buffers and a lot of final level clock buffers having a small number of fan-outs such as a single fan-out, thereby increasing the chip area, thus reducing the integration.

In FIG. 2, which illustrates a tree-type clock signal distributing circuit for explaining a logical tree synthesis method, clock buffers are arranged from a downstream side of a clock signal to an upstream side thereof (see T. Kimoto et al., "OpenCAD clock Tree Synthesis", NEC Technical Bulletin, Vol. 45 No. 8, pp. 16-20, 1992). That is, flip-flops are divided into classes. For example, flip-

flops

111 to 113 are allocated to a class K1; flip-

flops

121 to 123 are allocated to a class K2; and flip-

flops

131 to 133 are allocated to a class K3. In this case, the flip-flops allocated to each class are in the neighborhood of each other. Also, the number of flip-flops allocated to each class is the same, in this case, 3. Then, one final level clock buffer such as 11 is arranged at a substantial center position of each of the classes, and this clock buffer is connected by connections such as C₁₁₁, C₁₁₂ and C₁₁₃ to the flip-

flops

111, 112 and 113. Thereafter, the above-mentioned steps are repeated to obtain a two-storied hierachic configuration which is, however, not geometrically fixed. Thus, fan-outs of each clock buffer can be balanced to suppress the increase of the clock skew.

In FIG. 2, however, if the density of flip-flops is not homogeneous with the integrated circuit, the length of connections to the clock buffers fluctuates, so that the clock skew is increased. For example, as illustrated in FIGS. 3A-3C, in a region 3B where the density of flip-flops FF is relatively large, connections C1 between clock buffers B and flip-flops FF are short, while in a

region

3C where the density of flip-flops FF is relatively small, connections C2 between clock buffers B and flip-flops FF are long. Generally, the length of each connection is approximately in proportion to the square root of the density of flip-flops. Therefore, since the length of connections between the clock buffers and the flip-flops fluctuates in accordance with the density of flip-flops, the clock skew is increased.

In FIG. 4, which illustrates an

apparatus

40 for carrying out an embodiment of the method for arranging a tree-type clock signal distributing circuit according to the present invention, the

apparatus

40 is constructed by a computer which includes an input/output (I/O)

interface

401, a central processing unit (CPU) 402, a read-only memory (ROM) 403 for storing programs and fixed data, a random access memory (RAM) 404 for storing temporary data, and the like. The I/

O interface

401 receives various input signals from the

keyboard

41 and the like, and generates various signals and transmits them to a display such as a liquid crystal display (LCD) 42 and the like.

The operation of the

apparatus

40 of FIG. 4 will be explained with reference to FIGS. 5, 5A, 5B, 6, 7, 8, 9 and 10. Here, the present invention is applied to a 200 K gate standard cell base integrated circuit, as an example. Also, an area which requires no clock signal distributing line is omitted from the integrated circuit in advance.

Referring to FIGS. 5A and 5B, which show a main routine, at

step

501, the number N of stages of a clock tree, the number Mi of fan-outs of an i-th stage and the number R₀ of dummy flip-flops are determined by

M.sub.1 ×M.sub.2 ×. . . ×M.sub.N =M.sub.0 R.sub.0

M₀ is the total number of flip-flops. In this case, these values are determined so that the value N is minimum and the value R₀ is minimum. Also, 2≦M_i ≦FO_i (definite value) and R₀ ≧0. For example, if M₀ =32765, then,

N=5

M₁ =M₂ =M₃ =M₄ =M₅ =8

R₀ =3.

Next, at

step

502, the R₀ dummy flip-flops are inserted into adequate positions of the integrated circuit.

Next, at

step

503, the value i is initialized, i.e., i=1. In this case, a first stage of the clock tree on the downstream side thereof is indicated.

Next, at

step

504, an average density .sub.ρo of flip-flops within the integrated circuit is calculated.

Next, at

step

505, a multiplication constant n is initialized, i.e., n=2. This multiplication constant n will be used at

step

509.

Next, at step 506, the integrated circuit is divided into a number of square segments each having a length L which is a multiple of a grid length and is closest to n√M_i /.sub.ρo as shown in FIG. 6. In this case, note that, if there is a segment having a length smaller than L as indicated by

arrows

61 in FIG. 6, such a segment is united with its adjacent segment.

If the density of flip-flops within the integrated circuit is completely homogeneous, each segment includes M₁ ×n² flip-flops. As a result, n² clock buffers are allocated to each segment. However, actually, the density of flip-flops is not homogeneous.

Next, at

step

507, a density .sub.ρ of flip-flops within each of the segments is calculated. In this case, the segments having the density of 0 are omitted. Then, at step 508, a minimum value .sub.ρmin of the densities .sub.ρ is selected.

Next, at

step

509, it is determined whether or not

.sub.ρmin ≧.sub.ρo /n.sup.2

As a result, only when .sub.ρmin ≧.sub.ρo /n², does the control proceed to step 511. Otherwise, the control proceeds to step 510 which increases the multiplication constant n by +1, and then, the control at steps 506 through 509 is repeated.

step

511, the number p of classes of each segment is quantized in accordance with the minimum value .sub.ρmin of the densities .sub.ρ. This will be explained later in detail with reference to FIG. 7.

Next, at

step

512, the number of flip-flops allocated to each of the classes is determined. This will be also explained with reference to FIG. 8.

Next, at

step

513, flip-flops are allocated to the classes within each of the segments. In this case, a distribution of the flip-flops allocated to each class is homogeneous within the segment to which this class belongs. For example, the flip-flops within each of the segments are randomly selected and allocated sequentially to the classes thereof.

Next, at

step

514, one clock buffer is allocated to each of the classes. In this case, one clock buffer is inserted at a substantial center position, i.e., an arithmetic average position of the flip-flops of each of the classes, and is connected by connections to the flip-flops.

step

515, the value i is incremented by +1, and at

step

516, it is determined whether or not i>N is satisfied. Only when i>N, does the control proceed to step 518. Otherwise, the control proceeds the

step

517 which replaces the flip-flops with the clock buffers allocated at

step

514, and then return to step 504, thus repeating the above-mentioned

steps

504 through 514. In other words, the control at

steps

504 through 514 is repeated until the number of allocated clock buffers is one.

step

518, a final clock buffer which is finally arranged at a substantial center position of all of the flip-flops is connected by a connection to a clock driver (not shown) which receives an external clock signal or an internal clock signal derived from a control circuit (not shown).

Then, this routine of FIGS. 5A and 5B is completed by

step

519.

In FIG. 7, which is a detailed flowchart of

step

511 of FIG. 5, at

step

701, a segment area variable ₉₄ A and an input node number .sub.σN are initialized, i.e., .sub.σA =0 and .sub.σN =0. In this case, the input node number .sub.σN represents a number of flip-flops.

Next, at

step

703, a density of flip-flops for a segment S is calculated by

.sub.ρS ←N.sub.S /A.sub.S

where A_S is an area of the segment S; and N_S is the number of flip-flops within the segment S.

Next, at step 604, a value .sub.ρS /.sub.ρmin is calculated, and it is determined whether the value .sub.ρS /.sub.ρmin is an integer. Only when the value .sub.ρS /.sub.ρmin in an integer, does the control proceed to step 705 which causes the number p of classes to be .sub.ρS /.sub.ρmin. Otherwise, the control proceeds to step 706.

step

706, an integer p_L closest to the value .sub.ρS /.sub.ρmin but smaller is calculated, i.e.,

p.sub.L ←[.sub.ρS /.sub.ρmin ]

Also, at

step

706, an integer p_H closest to the value .sub.ρS .sub.ρmin but larger is calculated, i.e.,

p.sub.H ←p.sub.L +1

Next, at

step

708, a value .sub.σS ×.sub.ρo is compared with the input node number .sub.σN.

step

708, a value .sub.σS ×.sub.ρo <.sub.σN, the control proceeds to step 709 which causes the number p of classes to be p_L. Also, when .sub.σS ×.sub.ρo >.sub.σN, the control proceeds to step 710 which causes the number p of classes to be p_H. Further, when .sub.σS ×.sub.ρo =.sub.σN, the control proceeds to step 711.

step

711, a value .sub.ρS /.sub.ρmin -p_L is compared with a value p_H -.sub.ρS /.sub.ρmin.

step

711, when .sub.ρS /.sub.ρmin -p_L<p _H -.sub.ρS /.sub.ρmin, the control proceeds to step 709 which causes the number p of classes to be p_L. Also, when .sub.ρS /.sub.ρmin -p_L >p_H -.sub.ρS /.sub.ρmin, the control proceeds to step 710 which causes the number p of classes to be p_H. Further, when .sub.ρS /.sub.ρmin -p=p_H -.sub.ρS /.sub.ρmin, the control proceeds to step 712.

step

712, the number p of classes is caused to be p_L or p_H. In this case, the selection of p_L and p_H is carried out alternately or randomly.

The control at

step

705, 709, 710 and 712 proceeds to step 713 which increments the segment area variable .sub.σA and the input node number .sub.σN by

.sub.σA ←.sub.σA =A.sub.S

.sub.σN ←.sub.σN =N.sub.S

The control at

steps

703 through 713 is repeated by

steps

714 and 715 for all of the segments. In this case, a value S_max represents the number of segments.

Thus, at

step

716, the routine of FIG. 7 returns to step 512 of FIG. 5.

That is, in the routine of FIG. 7, the number p of classes within each of the segments is quantized so that the value .sub.σS /.sub.σN is brought close to the average density .sub.ρo.

In FIG. 8, which is a detailed flowchart of

step

512 of FIG. 5, at

step

801, the segment number S is initialized, i.e.,

S←1

step

802, a number N_S,i of flip-flops allocated to a class i of the segment S is calculated. In this case, the number N_S,i is determined so that the following value:

|.sub.σS,i..sub.ρo -.sub.σN,i |-|(.sub.σS,i +A.sub.S)..sub.ρo -(.sub.σN,i +N.sub.S,I)|

is brought close to a minimum value. Also, each value .sub.σS, i is a multiple of M_i.

The control at

step

802 is repeated by

steps

803 and 804 for all of the segments.

Then, this routine of FIG. 8 returns to step 513 of FIG. 5.

Thus, according to the routine of FIG. 8, as shown in FIG. 9, the value N_S,i is determined so that a point p_i (i=1 to p) is brought close to a dotted line indicated by DL.

According to the above-described embodiment, the flip-flops (clock buffers) belonging to each of the classes are arranged homogeneously within one segment to which this class belongs. In other words, the density of flip-flops (clock buffers) allocated to each class is close to the minimum value .sub.ρmin. For example, as illustrated in FIGS. 10A-10C, the length of connections C1 between a clock buffer B1 (B2, B3) and flip-flops FF1 (FF2, FF3) in a region 10B where the density of flip-flops FF is relatively large is about the same as that of connections C2 between clock buffers B and flip-flops FF in a region 10c were the density of flip-flops FF is relatively small. Thus, all of the connections for clock signal to the flip-flops do not fluctuate, i.e., are homogeneous.

As explained hereinbefore, according to the present invention, since all of the connections for a clock signal to functional blocks are homogeneous, the clock skew can be reduced.

Claims (11)

I claim:

1. A method for arranging a tree-type clock signal distributing circuit in a synchronous integrated circuit including a plurality of functional blocks, said method being performed by a processor which includes a central processing unit and a memory, said method comprising the steps of:

partitioning, by said central processing unit, said synchronous integrated circuit into a plurality of segments;

calculating, by said central processing unit, a density of said functional blocks within each of said segments and storing said density in said memory;

calculating, by said central processing unit, a minimum value of the stored densities of said functional blocks and storing said minimum value in said memory;

quantizing, by said central processing unit, the densities of functional blocks of said segments in accordance with the stored minimum value, so that said segments are divided into classes whose number is the same as a quantized density of each of said segments, and storing said classes of segments in said memory;

determining, by said central processing unit, the number of functional blocks belonging to each of said stored classes of segments;

allocating, by said central processing unit, said functional blocks within each of said segments to said classes thereof, so that a distribution of said functional blocks allocated to each of said classes is homogeneous within one of said segments to which the same class belongs, and storing said allocated functional blocks to said classes in said memory;

allocating, by said central processing unit, one clock buffer to a substantial center position of said functional blocks allocated to each of said classes, to connect said clock buffer to said functional blocks within each of said classes; and

repeating the above-mentioned steps by replacing said functional blocks with said clock buffers, until the number of clock buffers is one.

2. A method as set forth in claim 1, further comprising a step of calculating an average density of said functional blocks within said integrated circuit,

said segment dividing step comprising the steps of:

dividing said integrated circuit into a plurality of square areas as said segments, each area having a predetermined length multiplied by a multiplication constant;

calculating a density of said functional blocks within each of said square areas;

calculating a minimum value of the densities of said functional blocks within said square areas;

determining whether or not .sub.ρmin <.sub.ρo /n² where .sub.ρmin is the minimum value of the densities, .sub.ρo is the average density, and n is the multiplication constant;

increasing the multiplication constant only when .sub.ρmin <.sub.ρo /n² is satisfied; and

repeating said dividing, calculating, determining and increasing steps when the multiplication constant is increased.

3. A method as set forth in claim 2, further comprising a step of

determining a clock tree defined by M₁ ×M₂ ×. . . ×M_N =M₀ =R₀

where Mi(i=1, 2, . . . , N) is the number of fan-outs of an i-stage,

M₀ is the number of said functional blocks within said integrated circuit, and

R₀ is the number of dummy functional blocks;

allocating said dummy functional blocks to said synchronous integrated circuit,

the predetermined length of said squares being determined approximately by n.(M_i ρo)^1/2, when the i-stage of said clock tree is calculated.

4. A method as set forth in claim 3, wherein said clock tree determining step calculates the number M_i (i=1, 2, . . . , N) of fan-outs, so that the number N of stages is minimum and the number of said dummy functional blocks is minimum.

5. A method as set forth in claim 3, wherein said function block number determining step determines the number of said functional blocks of each of said classes in accordance with a multiple of M_i when the i-stage of said clock tree is calculated.

6. A method as et forth in claim 1, wherein said functional block allocating step allocates said functional blocks within each of said segments randomly to said classes thereof.

7. A method for arranging a tree-type clock signal distributing circuit in a synchronous integrated circuit including a plurality of functional blocks, said method being performed by a processor which includes a central processing unit and a memory, said method comprising the steps of:

determining, by said central processing unit, a clock tree defined by M₁ ×M₂ ×. . . X M_N =M₀ +R₀

where M_i (i=1, 2, . . . , N) is the number of fan-outs of an i-stage,

M₀ is the number of said functional blocks within said integrated circuit, and

R₀ is the number of dummy functional blocks;

allocating, by said central processing unit, said dummy functional blocks to said synchronous integrated circuit;

calculating, by said central processing unit, an average density .sub.ρo of said functional blocks within said synchronous integrated circuit;

partitioning, by said central processing unit, said integrated circuit into a plurality of square segments, each having a length determined by n.(M_i ρo)^1/2 where n is an integer larger than 1, when the i-stage of said clock tree is calculated;

calculating, by said central processing unit, a density of said functional blocks within each of said segments;

calculating, by said central processing unit, a minimum value of the densities of said functional blocks;

quantizing, by said central processing unit, the densities of functional blocks of said segments in accordance with the minimum value, so that said segments are divided into classes whose number is the same as a quantized density of each of said segments;

determining, by said central processing unit, the number of functional blocks belonging to each of said classes;

allocating, by said central processing unit, said functional blocks within each of said segments of said classes thereof, so that a distribution of said functional blocks allocated to each of said classes in homogeneous within one of said segments to which the same class belongs;

repeating said average density calculating step through said clock buffer allocating step by replacing said functional blocks with said clock buffer, until the number of said clock buffers is one.

8. A method as set forth in claim 7, wherein said clock tree determining step calculates the number M_i (i=1, 2, . . . , N) of fan-outs, so that the number N of stages is minimum and the number of said dummy functional blocks is minimum.

9. A method as set forth in claim 7, wherein said function block number determining step determines the number of said functional blocks of each of said classes in accordance with a multiple of M_i when the i-stage of said clock tree is calculated.

10. An apparatus for arranging a tree-type clock signal distributing circuit in a synchronous integrated circuit including a plurality of functional blocks, said apparatus including a processor, said apparatus comprising:

partitioning means for dividing said synchronous integrated circuit into a plurality of segments;

first calculating means for calculating a density of said functional blocks within each of said segments;

second calculating means for calculating a minimum value of the densities of said functional blocks;

quantizing means for quantizing the densities of functional blocks of said segments in accordance with the minimum value, so that said segments are divided into classes whose number is the same as a quantized density of each of said segments;

first allocating means for allocating said functional blocks within each of said segments to said classes thereof, so that a distribution of said functional blocks allocated to each of said classes is homogeneous within one of said segments to which the same class belong;

second allocating means for allocating one clock buffer to a substantial center position of said functional blocks allocated to each of said classes, to connect said clock buffer to said functional blocks within each of said classes; and

repeating means for replacing said functional blocks with said clock buffers, until the number of clock buffers is one.

11. An apparatus as set forth in claim 10, wherein the partitioning means, first calculating means, second calculating means, quantizing means, determining means, first allocating means, second allocating means, and repeating means are all performed by said processor.

US08/338,774 1993-11-10 1994-11-10 Method for arranging tree-type clock signal distributing circuit with small clock skew Expired - Fee Related US5519351A (en)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP5280996A JP2540762B2 (en)	1993-11-10	1993-11-10	Clock signal supply method
JP5-280996		1993-11-10

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US5519351A true US5519351A (en)	1996-05-21

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US08/338,774 Expired - Fee Related US5519351A (en)	1993-11-10	1994-11-10	Method for arranging tree-type clock signal distributing circuit with small clock skew