US6531377B2 - Method for high aspect ratio gap fill using sequential HDP-CVD - Google Patents

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Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
  • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Definitions

• the present invention relates generally to the fabrication of integrated circuits (IC's), and more particularly to the fabrication of memory IC's.
• DRAM dynamic random access memory
• a DRAM typically includes millions or billions of individual DRAM cells, with each cell storing one bit of data.
• a DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor.
• FET access field effect transistor
• the access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations.
• the data charges on the storage capacitor are periodically refreshed during a refresh operation.
• FRAM ferroelectric random access memory
• An FRAM typically has a similar structure to a DRAM but is comprised of materials such that the storage capacitor does not need to be refreshed continuously as in a DRAM.
• Common applications for FRAM's include cellular phones and digital cameras, for example.
• Insulating materials for example, SiO 2 are used to isolate conductors and other active regions in semiconductor devices.
• BEOL back-end-of-line
• PECVD plasma enhanced chemical vapor deposition
• TEOS tetraethoxysilane
• An anisotropic etch was used, such as a physical sputter etch, to remove the insulating material overhangs that covered areas that needed to be filled, and another insulating layer was deposited, e.g., by PECVD.
• HDP-CVD high density plasma chemical vapor deposition CVD
• BEOL back-end-of-line
• FEOL front-end-of-line
• STI shallow trench isolation
• FIG. 1 illustrates a prior art semiconductor device 10 having isolation trenches 11 formed in a substrate 12 , the isolation trenches 11 having a relatively high aspect ratio.
• the aspect ratio refers to the ratio of the height (h) compared to the width (w) between the isolation trenches 11 , and is expressed as a ratio of h:w, e.g., 3:1 or 4:1.
• the semiconductor device 10 in this example comprises a DRAM device, where the trenches 11 comprise isolation trenches (IT's) that are adapted to electrically isolate element regions of a DRAM chip, for example.
• the element regions may comprise active areas, storage capacitors, transistors, and other electronic elements, as examples.
• the process of forming IT's is often also referred to in the art as shallow trench isolation (STI), for example.
• STI shallow trench isolation
• a pad nitride 14 may be deposited over the substrate 12 .
• An insulating layer 16 is deposited over the semiconductor wafer 10 using HPD-CVD to fill the trenches between the active areas, as shown. Because of the high aspect ratio h:w which may be 2:1 or greater, the HDP-CVD process may result in voids 20 that form within the trenches 11 , as shown. This occurs because an insulator 16 deposited by HDP-CVD has a tendency to form cusps or huts 18 at the vicinity of the top portion of the trenches 11 .
• a problem in prior art isolation techniques is the formation of these voids 20 in high-aspect ratio trenches. Aggressive aspect ratios in DRAM devices are approaching 4:1 and greater.
• the gap fill requirement is a function of ground rule layout and critical dimension (CD) tolerances, for example.
• Voids 20 may inadvertently be filled with conductive material in subsequent processing steps such as gate conductor deposition, for example, which may short elements in the substrate.
• What is needed in the art is a method of providing isolation and depositing insulating material between high aspect ratio trenches in today's densely-packed semiconductor devices.
• the present invention achieves technical advantages as a method of filling high aspect ratio gaps in semiconductor devices.
• a first anisotropic insulating layer is deposited and etched with an isotropic etch to remove the first insulating from the sides of the trenches. Additional anisotropic insulating layers are deposited as required for the particular aspect ratio of the trench in order to fill the trench completely without leaving voids within the trench insulating material.
• a method of filling gaps between features of a semiconductor wafer, the gaps having sidewalls comprising depositing a first anisotropic insulating material over the wafer to partially fill the gaps, removing the first anisotropic insulating material from at least the gap sidewalls, and depositing a second anisotropic insulating material over the wafer to at least partially fill the gaps.
• the method comprises depositing a first insulating material over the isolation trenches, removing a portion of the first insulating material from at least over the isolation trench sidewalls, and depositing a second insulating material over the trenches.
• Advantages of embodiments of the present invention include providing a method of filling high aspect ratio gaps in semiconductors such as vertical FETs.
• a silicon nitride liner may be deposited over the trenches prior to the first insulating layer deposition so that an etch selective to nitride may be used to remove the first insulating layer from the side of trenches in an isotropic etch.
• the top portion of the silicon nitride liner may be removed prior to the deposition of the top insulating layer, which prevents divot formation on the top surface that may occur during the pad nitride removal. Because only one type of insulating deposition tool is required, the invention does not add an inordinate amount of complexity to the manufacturing process.
• An inexpensive process such as a wet etch process may be used to remove the insulating layers from the isolation trench sidewalls.
• the active areas of semiconductor devices are scalable in accordance with the present invention; that is, the number of insulating layers may be varied or increased in accordance with the trench aspect ratio required.
• FIG. 1 illustrates a cross-sectional view of a prior art DRAM having voids in the HDP-CVD insulating material between isolation areas or trenches;
• FIGS. 2-7 illustrate cross-sectional views of an embodiment of the present invention in various stages of manufacturing
• FIGS. 8-10 illustrate an embodiment of the present invention in various manufacturing stages
• FIG. 11 shows a cross-sectional view of another embodiment of the present invention.
• isolation trenches are shown in each figure, although many other isolation trenches and other memory cell components may be present in the semiconductor devices shown.
• FIGS. 2-7 An embodiment of the present invention is shown in cross-section in FIGS. 2-7.
• the semiconductor device 100 may comprise a DRAM or other memory device, or may alternatively comprise other types of semiconductor devices, as examples.
• the substrate 112 may comprise silicon or other semiconductor materials, for example.
• the substrate 112 may include element regions comprising active areas (AA's), storage capacitors and other electronic elements that need to be isolated from one another in the end product. To provide this isolation, isolation trenches 111 are formed within the substrate 112 .
• a pad oxide 122 may be formed over the substrate 112 .
• Pad oxide 122 typically comprises approximately 30-100 Angstroms of silicon oxide, for example.
• a pad nitride 114 may be deposited over the pad oxide 122 .
• Pad nitride 114 may comprise silicon nitride or other nitrides, for example, and may be approximately 1000 Angstroms thick.
• Isolation trenches 111 are then formed using a lithography and etch process.
• Trenches 111 may be 400-800 nanometers deep within the silicon 112 , for example, and have aspect ratios of 2:1, 3:1, 4:1 or greater.
• a sidewall oxide 121 is formed within isolation trenches 111 over the substrate 112 .
• the sidewall oxide 121 also referred to as an active area oxide (AA ox), preferably comprises thermally grown silicon oxide and may be approximately between 50 and 150 Angstroms thick.
• an optional nitride liner 125 is deposited within isolation trenches 111 over the pad oxide 121 .
• Nitride liner 125 preferably comprises silicon nitride and may alternatively comprise other nitrides, for example.
• the nitride liner 125 preferably is approximately 30-100 Angstroms thick.
• a first insulating material 116 is deposited over the wafer 100 within the isolation trenches 111 , as shown in FIG. 3 .
• First insulating material 116 preferably comprises SiO 2 and alternatively may comprise silicon nitride, oxynitride, silicon carbide, compounds thereof, phosphorous silicon-doped glass (PSG), or boron PSG (BPSG), as examples.
• first insulating material 116 is deposited in an anisotropic deposition process, such as HDP-CVD, so that only a small amount of insulating material 116 is deposited on the sides of the isolation trenches 111 , shown generally at 124 .
• the first insulating material 116 is deposited over the substrate 112 topography such that the first insulating material 116 thickness within the bottom of the trenches 111 exceeds the first insulating material 116 thickness on the sidewalls of the trenches 111 .
• the first insulating material 116 is preferably partially deposited within trenches 111 in a thickness of approximately 300 nanometers in the trench 111 bottom, for example.
• first insulating material 116 comprises an oxide, and because a nitride liner 122 is used, an etch selective to nitride is preferably used.
• a wet etch comprising buffered HF or other HF-based chemistries, or a dry isotropic etch, e.g. chemical downstream etching (CDE) using fluorine-based chemistries, may be used to remove the first insulating material 116 from the isolation trench 111 sidewalls, for example, when the insulating material 116 comprises SiO 2 .
• a timed etch may be used. Approximately 5-50 nanometers of first insulating material 116 is preferably removed.
• a second insulating material 126 is deposited over the wafer 100 , as shown in FIG. 5 .
• the second insulating layer 126 comprises oxide deposited by HPD-CVD.
• Second insulating material 126 preferably comprises SiO 2 and alternatively may comprise silicon nitride, oxynitride, silicon carbide, compounds thereof, PSG, or BPSG, as examples.
• the second insulating material 126 is preferably deposited using an anisotropic deposition process in order to deposit more insulating material 126 over the bottom of the isolation trenches 111 over the first insulating layer 122 than is deposited on the sides of the isolation trenches 111 .
• the second insulating layer 126 may be 400 nanometers, for example.
• a second isotropic etch process is performed on the wafer 100 , as shown in FIG. 6, to remove the second insulating material 126 from at least the sides of the trenches 111 .
• an oxide is used for second insulating material 126
• an etch selective to nitride may be used to remove the second insulating material 126 from the IT 111 sidewalls.
• a timed etch may be used. Approximately 10-100 nanometers of second insulating layer 126 is removed in the second etch step, for example.
• the second insulating material 126 thickness may be sufficient to completely fill the isolation trenches 111 to the top of the pad nitride 114 layer or greater.
• a chemical-mechanical polish CMP may be performed (not shown) to remove the undesired insulating material 116 and 126 from the top of the pad nitride 114 , and subsequent processing steps may be performed on the wafer 100 to complete the manufacturing process.
• the aspect ratio of the isolation trenches 111 is high, e.g. 3:1, 4:1 or greater, a total of three or more additional insulating material layers preferably deposited by HPD-CVD, may be required to fill the isolation trenches 111 and removed from at least the trench 111 sides, in sequential steps.
• the additional insulating material layers preferably comprise SiO 2 and alternatively may comprise silicon nitride, oxynitride, silicon carbide, compounds thereof, PSG, or BPSG, as examples.
• the additional insulating material layers are preferably deposited using an anisotropic deposition process in order to deposit more insulating material over the bottom of the isolation trenches 111 than is deposited on the sides of the isolation trenches 111 .
• the insulating material is removed from at least the isolation trench 111 sides using an isotropic etch, except for the last insulating material deposition.
• FIG. 7 shows a cross-sectional view of the wafer 100 having a third insulating material 130 deposited over the wafer 100 within trenches 111 .
• the third insulating material 130 is deposited using an anisotropic deposition process such as HDP-CVD to completely fill the isolation trenches 111 .
• a CMP is performed (not shown) to remove the undesired insulating material layers 116 / 126 / 130 from the top of the pad nitride 114 , and subsequent processing steps are performed on the wafer 100 to complete the manufacturing process.
• FIGS. 8-10 illustrate another embodiment of the present invention, where before the final insulating material layer 230 is deposited within the isolation trenches 211 , the nitride liner 225 is removed from the top region 242 of the trenches 211 .
• the nitride liner 225 is etched back, as shown in FIG. 8 .
• the nitride liner 225 etch is selective to oxide, and may comprise hot phosphoric acid, for example.
• the final insulating material layer 230 is deposited over the wafer 200 to fill the isolation trenches 211 , as shown in FIG. 9 .
• nitride liner 225 When the wafer 200 is polished by CMP to remove the excess insulating material 216 / 226 / 230 and pad nitride 214 is stripped, for example, by hot phosphoric acid, from the top of the substrate 212 , having removed the nitride liner 225 from the top portion of the isolation trenches 211 is advantageous because the formation of divots 229 along the silicon/insulator interface is prevented. If nitride liner 229 (shown in phantom) is left remaining in the top portion of isolation trenches 211 , divots 231 (shown in phantom) may form because silicon nitride 229 is partially removed during the pad nitride 214 strip.
• divots 231 in the top surface of the wafer 200 is undesirable because divots 231 may fill in subsequent deposition steps, e.g., of polysilicon, and create shorts.
• the removal of the SiN liner 229 improves the reliability of specific PFET devices due to reduced hot carrier degradation of their respective gate oxides.
• FIG. 11 shows an embodiment of the present invention having sequential layers of insulating material 316 / 32 / 330 deposited by HPD-CVD within isolation trenches 311 , without the use of a nitride liner 125 / 225 within the trenches.
• a timed etch is used to avoid damaging the oxide liner 321 that lines the active areas within the trenches 311 , for example.
• FIG. 11 also illustrates the isolation trenches 311 having an aspect ratio such that two insulating layers 316 / 326 are sufficient to fill the isolation trenches 311 .
• two or more insulating layers may be required to completely fill the gaps.
• the present invention is described herein as a method of filling isolation trenches in a memory device. However, the present method may also be utilized to fill gaps and provide electrical isolation between topographical features in any semiconductor device. The invention is particularly advantageous when the gaps or trenches have high aspect ratios, e.g. 3:1 or greater (3:1, 4:1, 5:1, etc.).
• the present invention achieves technical advantages as a method of filling high aspect ratios isolation trenches 111 / 211 / 311 with sequentially deposited layers of insulating material 116 / 126 / 130 / 216 / 226 / 230 / 316 / 326 that does not leave voids or gaps within the insulating material.
• Advantages of embodiments of the invention include providing a void-free method of filling high aspect ratio gaps in semiconductors such as vertical DRAMs.
• a silicon nitride liner 125 / 225 may be deposited over the isolation trenches 111 / 211 prior to the insulating material 116 / 126 / 130 / 216 / 226 / 230 deposition so that an etch process selective to nitride may be used to remove the insulating material 116 / 126 / 216 / 226 from the side of isolation trenches 111 / 211 in an isotropic etch.
• the top portion of the nitride liner 125 / 225 may be removed prior to the deposition of the top insulating material layer 130 / 230 , which prevents divot formation on the top surface that may occur during the pad nitride 114 / 214 removal.
• the invention does not add much complexity to the manufacturing process because only one type of insulating material deposition tool is required, and a wet etch process may be used to remove the insulating material 116 / 126 / 216 / 226 / 316 from the sides of the isolation trenches 111 / 211 / 311 , which is an inexpensive process.
• the active areas of semiconductor devices are scalable in accordance with the present invention, that is, the number of insulating material layers 116 / 126 / 130 / 216 / 226 / 230 / 316 / 326 may be varied or increased in accordance with the isolation trench 111 / 211 / 311 aspect ratio required.

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• Engineering & Computer Science (AREA)
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• Condensed Matter Physics & Semiconductors (AREA)
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• Semiconductor Memories (AREA)

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Citations (13)

• 2001
  • 2001-07-13 US US09/904,799 patent/US6531377B2/en not_active Expired - Lifetime
• 2002
  • 2002-06-27 DE DE10228691A patent/DE10228691A1/en not_active Ceased

Patent Citations (13)

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