US7557032B2 - Silicided recessed silicon - Google Patents

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  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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  • H10B12/05—Making the transistor
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  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0135—Manufacturing their gate conductors
  • H10D84/0137—Manufacturing their gate conductors the gate conductors being silicided
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  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0172—Manufacturing their gate conductors
  • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
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  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/03—Making the capacitor or connections thereto
  • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
  • H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
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  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
  • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2

Definitions

• This invention relates generally to silicidation reactions and the products thereof, and more particularly to the full silicidation of silicon in a recess.
• Integrated circuit designs are continually being scaled down in efforts to reduce power consumption and increase speed. With each passing generation, devices tend to get smaller and more densely packed, raising a variety of problems for integration.
• One of the problems for integration is the small volumes provided for conductive elements. In order to achieve acceptable circuit speeds, it is important that such elements are provided with very high conductivity.
• a method for forming a metal silicide structure in an integrated circuit.
• the method includes providing a recess within a partially fabricated integrated circuit. Silicon is deposited into the recess. A mixture of metals is deposited over the recess and in contact with the silicon, where the mixture of metals includes at least two metals having opposing diffusivities relative to silicon. The mixture of metals and the silicon are reacted in the recess to form a metal silicide within the recess.
• a method for forming a recessed access device for an integrated circuit.
• the method includes etching a trench in a semiconductor structure.
• the trench is lined with a dielectric layer, and the lined trench is at least partially filled with silicon.
• a metal layer is deposited over the trench and in contact with the silicon. The silicon in the trench is fully reacted in a silicidation reaction with the metal layer.
• an integrated circuit including a metal silicide structure.
• a metal silicide fills at least a lower portion of a recess without voids.
• the metal silicide includes a mixture of at least a first metal having a greater diffusivity in silicon than silicon has in the first metal.
• the metal silicide also includes a second metal having a lesser diffusivity in silicon than silicon has in the second metal.
• a memory device in accordance with another aspect of the invention, includes a recessed access device in a memory array, including a recess within a semiconductor substrate, a thin dielectric layer lining the recess, and a metal silicide filling at least a lower portion of the trench without voids.
• FIG. 1 is a schematic plan view of a memory device, laid out in accordance with a preferred embodiment of the invention.
• FIG. 2 is a schematic, cross-sectional side view of the memory device of FIG. 1 taken along lines 2 - 2 , in accordance with a preferred embodiment of the invention.
• FIGS. 3-7 are a series of cross-sectional views of a portion of a semiconductor device, illustrating formation of DRAM access transistors similar to those of FIGS. 1 and 2 , according to a preferred embodiment of the present invention.
• FIG. 8 is a schematic, cross-sectional view of the device of FIG. 7 after recessing silicon within the trench, and prior to deposition of metal for silicidation, in accordance with one embodiment of the present invention.
• FIG. 9 is a schematic, cross-sectional view of the device of FIG. 7 after planarizing silicon within the trench and depositing metal for silicidation, in accordance with another embodiment of the present invention.
• FIGS. 10A-11B are micrographs illustrating fully silicided, recessed gates for memory access devices after a silicidation anneal is performed on the device of FIG. 9 .
• FIG. 12 is a schematic cross-section showing the partially fabricated semiconductor device of FIGS. 10A-11B after recessing and burying the fully silicided gates within their trenches.
• FIGS. 13-21 are a series of cross-sectional views of a portion of a semiconductor device, illustrating simultaneous formation of peripheral transistor gate stacks and recessed access devices (similar to those of FIGS. 1 and 2 ) in the array, according to another embodiment of the invention.
• circuit design of these preferred embodiments may be incorporated into any integrated circuit.
• they may be advantageously applied to form any device having an array of electrical devices, including logic or gate arrays and volatile or non-volatile memory devices, such as DRAMs, RAMs, or flash memory.
• the integrated circuits formed by the methods described herein can be incorporated in any of a number of larger systems, such as motherboards, desktop or laptop computers, digital cameras, personal digital assistants, or any of a number of devices for which memory is useful.
• FIG. 1 shows a view of a portion of a memory device 10 .
• This schematic layout illustrates the various electrical devices and other components that form the memory device 10 .
• the memory device 10 is built on and in a substrate 11 , which forms the lowest level of semiconductor material in which electrical devices are formed.
• the substrate 11 typically comprises silicon.
• suitable materials e.g., other group III-V elements
• their depth or height may be most easily understood with reference to the top surface of the substrate 11 , best seen in FIG. 2 .
• word lines 12 a , 12 b , 12 c , 12 d are also shown in FIG. 1 extending along the memory device 10 .
• these word lines 12 were formed using a pitch doubling technique.
• these word lines 12 are preferably formed by a method that will be discussed in greater detail with reference to FIGS. 3-9 .
• the pitch of the resulting features may be less than the minimum pitch defined by the photolithographic technique.
• the pitch of the resulting features may equal one half the minimum pitch defined by the photolithographic technique.
• pitch doubling may be performed by the following sequence of steps, as is well understood by those skilled in the art.
• photolithography may be used to form a pattern of lines in a photoresist layer overlying a layer of an expendable material and a substrate.
• This photolithographic technique achieves a pitch between adjacent lines of 2F, as disclosed above, which pitch is limited by the optical characteristics of photolithography.
• F is within the range of 60 to 100 nm. This range is typical for state-of-the-art photolithographic techniques used to define features. In one photolithography system, F equals approximately 86 nm, while, in another system, F equals approximately 78 nm.
• each line defined by photolithography is typically also defined as F, as would be well understood by those skilled in the art.
• the pattern may then be transferred by an etching step (preferably anisotropic) to the lower layer of expendable material, thereby forming placeholders, or mandrels in the lower layer.
• the photoresist lines can then be stripped, and the mandrels can be isotropically etched to increase the distance between neighboring mandrels.
• the distance between the neighboring mandrels is increased from F to 3F/2.
• the isotropic “shrink” or “trim” etch could have been performed at the level of the resist.
• a conformal layer of spacer material may then be deposited over the mandrels.
• This layer of material covers both horizontal and vertical surfaces of the mandrels.
• Spacers i.e., material extending from sidewalls of another material, are therefore formed on the sides of the mandrels by preferentially etching the spacer material from the horizontal surfaces in a directional spacer etch.
• the remaining mandrels are then selectively removed, leaving behind only the spacers, which together may act as a mask for patterning.
• a given pitch, 2F formerly included a pattern defining one feature and one space
• the same width now includes two features and two spaces defined by the spacers.
• This method of pitch doubling which may be repeated for further reduction in the size of the features, will be discussed in greater detail below with reference to FIGS. 3-9 .
• the extent of the shrink/trim etch and the thicknesses of the deposited spacers may be varied to achieve a variety of feature and pitch sizes.
• the features i.e. word lines 12 in the instant example, have a pitch of F.
• the word lines 12 are defined by a width of about F/2, and adjacent word lines 12 a , 12 b or 12 c , 12 d are separated by the same width, F/2.
• the separation between the spaced-apart word lines 12 b , 12 c is 3F/2.
• an isolation trench is filled with an insulator and lies within this separation between these word lines 12 b , 12 c ; however, in other embodiments, this isolation trench need not be present.
• the word lines For every distance of 3F, there are two word lines, yielding what may be referred to as an effective pitch of 3F/2. More generally, the word lines preferably have an effective pitch between 1.25F and 1.9F. Of course, the particular pitch used to define the word lines is only an example. In other embodiments, the word lines may be fabricated by more conventional techniques, and pitch doubling need not be used. In one embodiment, for example, the word lines may each have a width of F and may be separated by F, 2F, 3F or some other width. In still other embodiments, the word lines need not be formed in pairs either. For example, in one embodiment, only one word line need pass through each active area.
• each word line 12 may extend across hundreds, thousands or millions of transistors.
• the word lines 12 are typically electrically coupled to a device, such as a power source, that can place a current across the word line 12 .
• the power sources for the word lines 12 are indirectly coupled to a CPU through a memory controller.
• the word lines 12 comprise a p-type semiconductor, such as silicon doped with boron. In other embodiments, the word lines 12 may comprise an n-type semiconductor, metal silicide, tungsten or other similarly behaving material, as is well-known to those of skill in the art. In some embodiments, the word lines 12 may comprise a variety of materials, in a layered, mixed or chemically bonded configuration.
• the horizontal lines seen in FIG. 1 are formed by digit lines 14 a , 14 b .
• the width of each of these digit lines, illustrated as DL in FIG. 1 is equal to F.
• No pitch doubling has been used to form these exemplary digit lines 14 .
• Adjacent digit lines 14 a , 14 b are separated, in a preferred embodiment, by a distance, illustrated as S in FIG. 1 , equal to 2F.
• the pitch of the digit lines is preferably greater than 2.5F, and preferably less than 4F. Without pitch-doubling techniques, the lower limit is, of course, imposed by the photolithographic technique used to form the digit lines.
• the pitch of the digit lines is between 2.75F and 3.25F. This range represents a desirable balance between the ease of manufacturing and the size of the chip.
• the digit lines 14 have a pitch of 3F. Of course, in other embodiments, different widths and spacing are possible.
• the entire length of the digit lines 14 is also not visible in FIG. 1 , and the digit lines 14 typically extend across many transistors.
• the digit lines 14 are typically electrically coupled to current sense amplifiers, and thereby to a power or voltage source.
• the power sources for the digit lines 14 are also indirectly coupled to a CPU through a memory controller.
• the sense amplifiers may be spaced farther from one another, relaxing their manufacturing tolerances, and decreasing the likelihood of capacitance coupling of adjacent digit signals.
• the digit lines 14 comprise a conducting metal, such as tungsten, copper, or silver. In other embodiments, other conductors or semiconductors may be used, as is well-known to those of skill in the art.
• the other features visible in FIG. 1 are the active areas 16 , illustrated within curvilinear rectangles, which form axes A that are angled relative to the axes B of the digit lines. These rectangles represent a doped region or well within the substrate 11 ; however, in other embodiments, these rectangles need not represent physical structures or materials within or upon the memory device 10 and substrate 11 .
• the active areas 16 define those portions of the memory device 10 that contain field effect transistors and are typically surrounded by field isolation elements (e.g., shallow trench isolation (STI)).
• these active areas each comprise two drains 18 and one source 20 .
• the source and drains may be larger or smaller than illustrated in FIG. 1 , as is well known to those of skill in the art. They may also be fabricated in any of a number of ways well-known to those of skill in the art.
• the active areas may comprise one source and one drain, wherein the source is formed near the digit line, and the drain is separated from the source by a word line.
• the memory device may be configured similarly to the memory device 10 in FIG. 1 , but there need only be one word line passing through each active area.
• an active area may comprise one source and one drain, and the memory device may further comprise two word lines extending near the active area, configured similarly to the paired word lines 12 c , 12 d shown in FIG. 1 .
• the two word lines may both extend between the source and drain, and provide redundant control of the transistor.
• a digit line 14 runs proximal to, and preferably above (see FIG. 2 ), each source 20 that lies in the digit line's row. Meanwhile, each source 20 is separated to either side from its adjacent drains 18 by word lines 12 .
• the source 20 and drains 18 comprise an n-type semiconducting material, such as silicon doped with phosphorous or antimony.
• the source 20 and drains 18 may comprise a p-type semiconductor, or they may be fabricated from other materials, as is well-known to those of skill in the art. In fact, the source 20 and drains 18 need not be fabricated from the same compounds.
• FIG. 2 shows a cross-sectional view of one of the active areas 16 .
• FIG. 2 shows a cross-sectional view of one of the active areas 16 .
• the drains 18 and source 20 may comprise protrusions from the relatively flat, upper surface of the substrate 11 .
• the source 20 and drains 18 are fabricated as one-piece with the substrate 11 , and are raised relative to the surface of the substrate 11 by etching a monolithic wafer or substrate; in another arrangement, the source and drain protrusions are formed by selective epitaxial deposition using techniques well-known to those of skill in the art.
• digit line 14 b is located above the upper surface of source 20 .
• the source 20 is electrically coupled to the digit line 14 b by a digit line plug 22 , which plug may be formed in multiple stages or in a single stage, as shown.
• the source 20 is separated from the two drains 18 by word lines 12 a , 12 b .
• the word lines 12 a , 12 b are preferably embedded in the substrate 11 , extending downwards from the surface. Transistors of this design are often referred to as recessed access devices or RADs.
• the drains 18 are, in turn, electrically coupled to storage capacitors 24 , and, in particular, to the lower electrode 26 of the storage capacitors 24 , by contact plugs 28 .
• the storage capacitors 24 comprise a lower electrode 26 separated from a reference electrode 30 by a dielectric material 32 . In this configuration, these stacked storage capacitors 24 function in a manner well known to those of skill in the art. As illustrated, the storage capacitors 24 are preferably located above the plane of the substrate 11 , although trench capacitors can be used in other arrangements.
• every storage capacitor 24 forms a reference electrode 30 , while the lower electrode 26 is electrically coupled to an associated drain 18 .
• the word lines 12 a , 12 b function as gates in the field effect transistors they pass through, while the digit line 14 b functions as a signal for the sources to which it is electrically coupled.
• the word lines 12 a , 12 b preferably control access to the storage capacitors 24 coupled to each drain 18 , by allowing or preventing the signal (representing a logic “0” or a logic “1”) carried on the digit line 14 b to be written to or read from the storage capacitors 24 .
• each of the two capacitors 24 connected to an associated drain 18 can contain one bit of data (i.e., a logic “0” or logic “1”).
• a logic “0” or logic “1” In a memory array, the combination of the digit line and word line that are selected can uniquely identify the storage capacitor 24 to or from which data should be written or read.
• Axis A represents the longitudinal axis of active area 16 .
• the drains 18 and source 20 of each active area 16 preferably have a substantially linear relationship that may be used to define a longitudinal axis. As illustrated, all of the active areas 16 are substantially parallel. It will be understood, of course, that the drains 18 and source 20 need not form an absolutely straight line, and indeed a substantial angle may be defined by these three points.
• the axis A may be defined by the two drains 18 , or by the source 20 and only one of the drains 18 , or in a number of other ways that would be clearly understood by those skilled in the art.
• the axis A may be defined by a line between the single drain and single source.
• Axis B represents the longitudinal axis of digit line 14 b .
• the digit line 14 b forms a substantially straight line.
• the digit lines 14 a , 14 b also preferably form generally parallel axes.
• axis A of every active area 16 forms a similar angle with every axis B of the digit lines 14 , at least in the region of each memory cell.
• an acute angle is formed between axis A and axis B.
• this acute angle, ⁇ defined between axis A and axis B, is 45°.
• the angling of the active areas 16 relative to the digit lines 14 facilitates the location of the contact plugs 28 extending between drains 18 and associated storage capacitors 24 . Since these contact plugs 28 extend from the top surface of the drains 18 in the preferred embodiment (illustrated in FIG. 2 ), the engineering is simplified if the digit lines 14 do not extend over the tops of the drains 18 .
• the distance between a digit line 14 and drains 18 may be selected to facilitate electronic contact between the drains and contact plugs, even while the digit line 14 substantially overlaps and contacts the source 20 of the same active area 16 .
• the angle, ⁇ may have any of a number of values chosen to maximize the pitch of the electrical devices. As will be readily apparent to one of skill in the art, different angles will yield different pitches between adjacent active areas.
• the angle, ⁇ is preferably between 10° and 80° degrees. In a more preferred embodiment, the angle, ⁇ , is between 20° and 60°. In a still more preferred embodiment, the angle, ⁇ , is between 40° and 50°.
• FIG. 3 illustrates a semiconductor substrate 11 over which a thin, temporary layer 40 , comprising oxide in a preferred embodiment, has been formed according to conventional semiconductor processing techniques.
• a hard mask layer 42 such as silicon nitride, is then deposited over the substrate 11 and temporary layer 40 .
• the hard mask layer 42 may be formed by any well-known deposition process, such as sputtering, chemical vapor deposition (CVD) or low-temperature deposition, among others.
• CVD chemical vapor deposition
• the hard mask layer 42 comprises silicon nitride in the preferred embodiment, it must be understood that it may also be formed of silicon oxide, for example, or other materials suitable for the selective etch steps described below.
• the hard mask layer 42 is patterned using a photoresist layer formed over the hard mask layer 42 .
• the photoresist layer may be patterned to form a mask using conventional photolithographic techniques, and the hard mask layer 42 may then be anisotropically etched through the patterned photoresist to obtain a plurality of hard mask columns 44 extending in the y-dimension (as defined by FIG. 1 ), with trenches 46 separating those columns.
• the photoresist layer may then be removed by conventional techniques, such as by using an oxygen-based plasma.
• a conformal layer of spacer material may be deposited to cover the entire surface of the memory device 10 .
• the spacer material can be selectively etched with respect to the substrate 11 and the temporary layer 40 , and the substrate 11 and the temporary layer 40 can each be selectively etched with respect to the spacer material.
• the spacer material comprises polysilicon.
• the spacer material may be deposited using any suitable deposition process, such as, for example, CVD or physical vapor deposition (PVD).
• an anisotropic etch may be used to preferentially remove the spacer material from the horizontal surfaces in a directional spacer etch.
• the spacer material is formed into spacers 48 , i.e., material extending from the sidewalls of another material. As shown in FIG. 5 , spacers 48 are formed within the trench 46 and narrow it.
• a second hard mask layer 49 may then be deposited over the entire surface of the memory device 10 .
• This layer of hard mask 49 also silicon nitride in a preferred embodiment, is preferably deposited to a thickness sufficient to fill the trench 46 .
• the hard mask material 49 may be deposited by any of a number of suitable deposition processes, including CVD or PVD. After deposition of a sufficient amount of hard mask material 49 , the excess that may have formed over the spacers 48 and over the other portions of previously deposited hard mask 42 may be removed by any of a number of processes well-known to those of skill in the art.
• the surface of the device 10 may be planarized to the level of the dotted line of FIG. 5B , such that the sidewalls of the remaining spacers 48 are nearly vertical. Any suitable planarization process, such as, for example, chemical mechanical planarization may be used.
• the spacers 48 that are now exposed at the top surface of the memory device 10 may be stripped using any of a number of processes.
• a process may be used that selectively strips polysilicon relative to silicon nitride.
• a selective wet etch may be used.
• the trenches formed where the spacers 48 have been etched are further deepened by a secondary etch that selectively etches the temporary layer 40 as well as the substrate 11 .
• These trenches are also preferably formed using a directional process, such as, for example, ion milling or reactive ion etching.
• FIG. 6 illustrates the result of these processes, with openings or recesses in the form of trenches 50 separated by less than the minimum pitch possible using photolithographic techniques alone.
• the trenches 50 Preferably have a width at top between about 25 nm and 75 nm.
• numerous other techniques for pitch multiplication may be used to arrive at the stage shown in FIG. 6 .
• Many such techniques will generally include a spacer process, by which physical deposition can achieve a smaller pitch than photolithographic techniques alone.
• the trenches 50 typically also have an aspect ratio greater than 1:1, and preferably greater than 2:1. Increased depth maximizes available volume and thence conductivity for the word lines, at the expense of difficulty in filling with a suitable material.
• a gate dielectric layer 54 is blanket deposited or thermally grown over the device, lining the inner surfaces of the trenches 50 .
• the illustrated gate dielectric layer 54 comprises silicon oxide formed by thermal oxidation in a preferred embodiment, but can also be a deposited high K material in other embodiments.
• a layer of gate material 52 which comprises polysilicon in the illustrated embodiment, may then also be blanket deposited over the entire memory device 10 .
• the gate layer 52 completely fills the trenches 50 and forms a top surface of the device 10 . In a preferred embodiment, this polysilicon is undoped.
• the undoped polysilicon in the trenches 50 is etched back until the top of the gate layer 52 resides beneath the top surface of the substrate 11 . This stage of the process is shown in FIG. 8 .
• the recessed polysilicon 52 of FIG. 8 can serve as the word lines and the gate electrodes for the memory cell transistors if appropriately doped.
• the gate electrodes in the arrays are formed of a more highly conductive material than traditional polysilicon gates. This is due to the fact that the recessed gates 12 (see FIGS. 1 and 2 ) are more narrow than the typical gate electrode. Metallic materials compensate, in whole or in part, for the small volume of the gates in the array, improving lateral signal propagation speed along the word lines.
• the undoped polysilicon of FIG. 8 can be silicided after recessing by depositing metal thereover and reacting. Metal silicide can have better than 10 times the conductivity of doped polysilicon and demonstrate a suitable work function.
• the polysilicon 52 is initially etched back or planarized down to the gate oxide 54 , thus isolating the polysilicon within the trenches 50 without recessing at this stage.
• the polysilicon of the gate layer 52 within the trenches 50 is subjected to a salicidation (self-aligned silicidation) reaction to form a layer of conductive material 56 .
• a metal layer 55 ( FIG. 9 ) may be blanket deposited and an anneal step may form a silicide material 56 ( FIG. 12 ) wherever the metal contacts silicon, such as over the polysilicon gate layers 52 .
• the silicided material comprises silicon and one or more metals, such as, for example, tungsten, titanium, ruthenium, tantalum, cobalt or nickel.
• a selective metal etch removes the excess metal but does not remove the silicide 56 .
• the metal silicide 56 thereby forms a self-aligned layer that increases the lateral conductivity along the word line.
• the gate layer 52 is fully silicided to maximize lateral conductivity. Full reaction also assures silicide formation down to the bottom of the trenches 50 .
• the channel extends across not only the bottom of the gate, but also along the gate's sidewalls. Accordingly, incomplete silicidation would result in different work functions along the length of the RAD channel.
• full silicidation ensures similar gate work functions across the array, from array to array across a wafer, and from wafer to wafer. It has been found difficult, however, to achieve full silicidation within the tight confines of the illustrated trenches 50 , with a single metal to form the conductive material 56 .
• Other metals have demonstrated similar difficulties for full silicidation for recessed access devices. The skilled artisan will appreciate that full silicidation can be challenging for material within other types of recesses, such as contact openings or vias, stacked container shapes for capacitors, capacitor trenches, etc.
• the voiding appears to be caused by diffusion during the silicidation reaction, in combination with the tight confines of the high aspect ratio trenches 50 .
• Silicon diffuses more readily in cobalt than cobalt does into silicon. Accordingly, silicon tends to migrate during the reaction, leaving voids in the trenches 50 .
• Nickel diffuses more readily into silicon than silicon does into nickel and so also has a tendency to create voids during the reaction in which NiSi is converted into the NiSi 2 phase.
• the metal layer 55 preferably comprises a mixture of metals, where at least two of the metals in the mixture have opposing diffusivities relative to silicon.
• the metal layer 55 can comprise a mixture of nickel and cobalt, such that the directions of diffusion tend to balance each other and minimize the risk of voiding.
• the cobalt preferably comprises less than 50 at. % of the mixed metal 55 , and more preferably the mixture comprises about 70-90 at. % Ni and about 10-30 at. % Co.
• Such a mixture of nickel and cobalt has been found to more readily accomplish full silicidation of the gate layer without voiding, thus increasing signal propagation speeds along the word line.
• fully silicided word lines are not only more conductive, but also will ensure consistent work function along the length of the channel. Full silicidation will also demonstrate better consistency from device to device across an array, from array to array, or wafer to wafer, since partial silicidation will tend to leave inconsistent compositions depending upon local temperature variations, etc.
• a sputtering target comprising 80% Ni and 20% Co is sputtered over the polysilicon 52 to produce the metal layer 55 .
• the substrate is then subjected to a silicidation anneal. While a high temperature (e.g., 800° C.) anneal is possible for a shorter time, preferably the anneal is conducted at lower temperatures for a longer time. For example, the substrate is annealed at 400-600° C. for 25-35 minutes. In experiments, the silicidation anneal was conducted in a batch furnace under an N 2 environment at 500° C. for 30 minutes.
• metals that diffuse more readily in silicon than silicon does in that metal include Ni, Pt and Cu.
• metals in which silicon diffuses more readily than the metal diffuses in silicon include Co, Ti and Ta.
• FIGS. 10A-11B are micrographs showing recessed, fully silicided Ni x Co y Si z gate material within 50 nm wide trenches lined with silicon oxide.
• FIGS. 10A and 10B show cross sections across the width of twin trenches, at two different magnifications.
• FIGS. 11A and 11B show cross sections along the length of one of the trenches, at two different magnifications.
• the trenches have a width at the top of about 50 nm and a depth of about 150 nm, such that the aspect ratio of these trenches was about 3:1.
• a smooth, uniform composition is observed, filling at least a lower portion of the trenches without voiding.
• FIGS. 11-12 after depositing the polysilicon 52 ( FIG. 7 ), the polysilicon can be etched back only to the gate dielectric top surface 54 , thus isolating the silicon within the trenches without recessing.
• the silicided layers 56 can be recessed within the trenches and are then covered by a second insulating layer 58 , such as silicon nitride. These insulating layers 58 may be deposited and then etched or planarized.
• the conductive material 56 thereby forms the word lines 12 a , 12 b of the completed memory device 10 , and the word lines 12 a , 12 b are separated from the other circuit elements by the insulating layers 58 .
• the word lines 12 have been pitch-multiplied, and have a pitch roughly one half of that possible simply using photolithographic techniques. Note, however, that certain aspects of the disclosure herein provide advantages whether or not the word lines are pitch-multiplied.
• the pitch-multiplication may take place by any of a variety of processes well-known to those skilled in the art.
• the silicided layers 56 of the illustrated embodiment thus fill lower portions of the trenches 50 , preferably filling greater than 50% of the trench heights, more preferably filling greater than 75% of the trench height.
• about 70-90 at % of metal in the metal silicide 56 is nickel and about 10-30 at % of metal in the metal silicide is cobalt.
• the logic in the periphery is preferably simultaneously defined as certain of the above steps are completed, thereby making the chip-making process more efficient.
• the silicon and metal deposition steps to define recessed word lines preferably simultaneously define gate electrodes over the substrate for the CMOS transistors in the periphery.
• different work functions and resistivity can be established for the simultaneously processed gate electrodes in the array and the logic regions in the periphery. In the illustrated embodiment, this is facilitated by etching array RAD trenches through a polysilicon layer, which forms part of the gate stack in the periphery.
• a polysilicon layer 60 can be deposited over the substrate 11 prior to forming the trenches.
• the polysilicon layer 60 can be first deposited over a thin dielectric 54 a (e.g., grown gate oxide).
• the substrate can then be patterned with a pitch-doubled mask (not shown), such as that described with respect to FIGS. 3-6 .
• An etch stop layer 61 is also formed, in the illustrated embodiment comprising about 100-200 ⁇ of TEOS-deposited oxide.
• the trenches 50 are etched through the overlying etch stop layer 61 , the polysilicon layer 60 , the underlying dielectric 54 a and the substrate 11 .
• the gate dielectric 54 b can then be formed over the exposed portions of the substrate 11 , such as by oxidation of the trench walls. Due to the pre-existing etch stop layer 61 , no significant further oxide grows over the top surface of the polysilicon 60 , as shown.
• a metallic material 62 can be deposited over the polysilicon 60 and into the trenches 50 .
• the trenches 50 are preferably filled with material more conductive than polysilicon.
• the metallic material 62 comprises titanium nitride (TiN).
• the metallic material 62 is preferably etched back or planarized to leave isolated lines of the conductive material 62 in the trenches 50 , stopping on the oxide etch stop layer 61 (see FIG. 15 ).
• the etch stop layer 61 overlying the polysilicon layer 60 is removed (e.g., using an HF dip for the preferred oxide material of the etch stop layer 61 ), while the dielectric layer 54 b within the trenches 50 is protected by the metallic material 62 .
• metallic layers 64 , 66 are deposited over the silicon layer 60 .
• the first dielectric layer 54 a , the polysilicon layer 60 , and the overlying metallic layers 64 , 66 can serve as the transistor gate stack in the periphery. All these layers are deposited in both regions of interest (in the memory example, in both periphery and memory array regions).
• Polysilicon can be variably doped to establish a desired transistor work function, such that a single material deposition, and different doping steps, can be used to define gates for both NMOS and PMOS of a CMOS circuit.
• the overlying metallic layer 66 can serve to improve lateral signal propagation speeds along lines controlling the gates, and comprises tungsten (W) in the illustrated embodiment.
• the intervening metallic layer 64 can ensure physical and electrical compatibility (e.g., fulfilling adhesion and barrier functions) at the juncture between the polysilicon layer 60 and the overlying metallic layer 66 , and in the illustrated embodiment comprises titanium nitride, and more particularly metal-rich metal nitride.
• the gate stack also includes a cap layer 68 , formed of silicon nitride in the illustrated embodiment.
• FIG. 17 shows the trenches 50 , filled with the metallic material 62 , in a first or memory array region 70 of the substrate.
• the gate stacks layers 54 a , 60 , 64 , 66 and 68 extend across both the array region 70 and the second or periphery or logic region 72 of the substrate.
• a photoresist mask 76 is configured for patterning transistor gates in the periphery 72 .
• a series of etch steps etches first through the cap layer 68 , including a metal etch to remove the metallic layer(s) 64 , 66 .
• Chlorine-based reactive ion etch (RIE) for example, can selectively remove typical metallic materials, such as the illustrated tungsten strapping layer 66 and intervening metal nitride layer 64 , while stopping on the underlying polysilicon layer 60 .
• RIE reactive ion etch
• a high degree of selectivity enables continuing the metal etch after exposure of the polysilicon 60 until the metallic material 62 is recessed in the trenches 50 , as shown.
• the etch chemistry can be switched following recessing of the metallic gate material 62 in the array trenches, and the silicon 60 can be patterned using the same mask 76 , completing patterning of the gate stacks 80 for the periphery 72 .
• a spacer layer 84 is deposited over the substrate, coating the gate stacks 80 conformally but filling the recesses at the top of the array trenches 50 .
• the spacer layer 84 comprises silicon nitride, but the skilled artisan will appreciate that a number of different insulating materials can be used.
• a subsequent spacer etch leaves sidewall spacers 86 along sidewalls of the gate stacks 80 , allowing self-aligned doping of source/drain areas.
• the spacer etch merely etches the spacer material back in the array 72 , leaving an insulating cap layer 88 burying the gate material 62 within the trenches 50 .
• CMOS transistors including source/drain, channel enhancement, gate electrode, lightly doped drain (LDD) and halo doping, are omitted in the description herein for simplicity.
• LDD lightly doped drain
• FIGS. 13-21 thus facilitates simultaneous processing of transistors in the array and the periphery.
• the array transistors are recessed access devices (RADs), whereas the peripheral gates are formed above the substrate 11 as conventional planar MOS transistors. While described in the context of conventional CMOS circuitry in the periphery, the skilled artisan will appreciate that the peripheral transistors can take other forms.
• the metallic layer in the RAD trenches can be recessed at the same time as patterning the peripheral gate stacks.
• the peripheral sidewall spacers are simultaneously formed with the insulating cap on the RAD gates or word lines.
• DRAM fabrication techniques may be used to create the other circuit elements shown in FIG. 2 .
• different levels of doping may be used to form the drains 18 and source 20 of FIG. 2
• the stacked storage capacitors 24 may be formed according to a plurality of deposition and masking steps.
• the completed memory device 10 shown in FIGS. 1 and 2 possesses a number of advantages in comparison to conventional DRAM.
• the size of each memory cell and the overall size of the memory device 10 may be substantially reduced without a corresponding, substantial reduction in the distance between adjacent sense amplifiers.
• the word lines 12 and digit lines 14 may have substantially different pitches, which enables the digit lines 14 to have far greater separation than the word lines 12 .
• the word lines 12 have an effective pitch of 1.5F, while the digit lines 14 may have a pitch of 3F.
• the steps for forming the digit lines 14 and word lines 12 are simplified by making them substantially linear and generally perpendicular to one another, while realizing space-savings by placing the active areas 16 at an angle to these elements.
• the word lines 12 in the preferred embodiment are also recessed, and, unlike the layout in conventional DRAM, there is no spacer using up valuable space between the gates and the sources or drains of the active areas (as may be easily seen in FIG. 2 ). Thus, the memory device 10 may be made more dense.
• the use of a mixture of metals facilitates full silicidation of the silicon buried within trenches 50 without the harmful formation of voids. Accordingly, a high conductivity can be achieved for the relatively small volume word lines.

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