US7957206B2 - Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same - Google Patents

Images

Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
  • G11C7/067—Single-ended amplifiers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
  • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4094—Bit-line management or control circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
  • G11C2207/06—Sense amplifier related aspects
  • G11C2207/063—Current sense amplifiers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
  • G11C2207/10—Aspects relating to interfaces of memory device to external buses
  • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C2211/4016—Memory devices with silicon-on-insulator cells

Definitions

• the present inventions described and illustrated herein relate to an integrated circuit device having a memory cell array and read circuitry to detect, sense, sample and/or determine a data state of the memory cells in the array. More particularly, in one aspect, the present inventions relate to an integrated circuit having memory cell array including a plurality of memory cells (for example, memory cells having an electrically floating body in which a charge is stored) wherein read circuitry is selectively coupled to one or more memory cells to detect, sense, sample and/or determine a data state of the one or more memory cells.
• memory cell array including a plurality of memory cells (for example, memory cells having an electrically floating body in which a charge is stored) wherein read circuitry is selectively coupled to one or more memory cells to detect, sense, sample and/or determine a data state of the one or more memory cells.
• memory cell array 10 typically includes a plurality of memory cells 12 arranged in a matrix of rows and columns.
• a row address decoder enables one or more rows to be read by sensing circuitry (for example, a plurality of sense amplifiers).
• a column decoder in response to an address, selects one or more of the outputs of the data sensing circuitry.
• the memory cell may consist of a partially depleted (PD) or a fully depleted (FD) SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric.
• the body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region.
• the state of cell is determined by the concentration of charge in the body of the transistor.
• memory cell array 10 may include a plurality of memory cells 12 , each consisting of (or consisting essentially of) transistor 14 having gate 16 , an electrically floating body region 18 , source region 20 and drain region 22 .
• the electrically floating body region 18 is disposed between source region 20 and drain region 22 .
• body region 18 is disposed on or above region 24 , which may be an insulation region (for example, a silicon dioxide or silicon nitride material of an SOI material) or non-conductive region (for example, in bulk-type material).
• the insulation or non-conductive region may be disposed on substrate 26 .
• Source line ( 30 ) is a common node in a typical implementation though it could be similarly decoded.
• charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18 .
• U.S. Pat. Nos. 6,969,662, 7,301,803 and U.S. Patent Application Publication No. 2007/0058427 including, for example, all features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
• memory cell 12 of memory cell array 10 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 34 from body region 18 of, for example, N-channel transistors.
• accumulating majority carriers (in this illustrative example, “holes”) 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22 is representative of a logic high or “ 1 ” data state.
• Emitting or ejecting majority carriers 34 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction is representative of a logic low or “ 0 ” data state. (See, FIG. 3B ).
• the sense amplifier typically includes an input/output connected to an associated bit line and an input connected to a reference current generator.
• the sense amplifier compares the current conducted by the memory cell with a reference current.
• the magnitude of the reference current generally lies between the magnitudes of the currents conducted in the logic high data state and logic low data state of the memory cell.
• the sense amplifier compares the reference current to the current produced by the memory cell (the current varies depending on whether the memory cell is either in a logic high data state or logic low data state).
• the sense amplifier Based on that comparison, the sense amplifier generates or outputs an output signal having a predetermined polarity (for example, a positive or negative polarity) depending on the data state stored in the memory cell (for example, whether the memory cell stored a logic high or a logic low binary data state).
• a predetermined polarity for example, a positive or negative polarity
• the data state stored in the memory cell for example, whether the memory cell stored a logic high or a logic low binary data state.
• each memory cell includes an electrically floating body transistor including a body region which is electrically floating, wherein each memory cell is programmable to store one of a plurality of data states including (i) a first data state representative of a first charge in the body region of the transistor, and (ii) a second data state representative of a second charge in the body region of the transistor.
• the integrated circuit device further includes memory cell control circuitry, coupled to the memory cell array, to generate one or more read control signals to perform a read operation wherein, in response to the one or more read control signals, the electrically floating body transistor associated with a selected memory cell conducts a current, which is representative of the data state stored in the selected memory cell, on the bit line.
• the integrated circuit device also includes sense amplifier circuitry having an input which is electrically coupled to the bit line to receive a signal which is responsive to the current conducted on the bit line by the electrically floating body transistor of the selected memory cell and, in response thereto, to (i) sense the data state stored in the selected memory cell and (ii) output a signal which is representative thereof.
• Current regulation circuitry electrically coupled to the bit line, sinks or sources at least a portion of the current conducted on the bit line by the electrically floating body transistor of the selected memory cell during only a portion of the read operation.
• sensing circuitry coupled between the bit line and the current regulation circuitry, responsively couples the current regulation circuitry to the bit line during the portion of the read operation.
• the sensing circuitry includes a transistor (for example, a p-channel or n-channel type transistor) wherein the transistor provides a current path between the bit line and the current regulation circuitry in response to a predetermined voltage on the bit line.
• the sensing circuitry includes a switch which provides a current path between the bit line and the current regulation circuitry in response to a predetermined voltage on the bit line.
• the sense amplifier circuitry may sense the data state of the selected memory cell using an amplitude of the voltage on the bit line.
• the amplitude of the voltage on the bit line is responsive to the amount of current on the bit lineconducted by the electrically floating body transistor associated with the selected memory cell during the read operation.
• the current regulation circuitry includes a current mirror circuit.
• the electrically floating body transistor associated with the selected memory cell may conduct a channel current which is representative of the data state of the memory cell on the bit line.
• the electrically floating body transistor associated with the selected memory cell may conduct a bipolar transistor current which is representative of the data state of the memory cell on the bit line.
• the present inventions may be directed to an integrated circuit device comprising a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell is programmable to store one of a plurality of data states, and a bit line having an intrinsic capacitance, wherein a plurality of the memory cells are coupled to the bit line.
• the integrated circuit device may include memory cell control circuitry, coupled to the memory cell array, to generate one or more read control signals to perform a read operation wherein, in response to the one or more read control signals, a selected memory cell conducts a current, which is representative of the data state stored in the selected memory cell, on the bit line.
• Sense amplifier circuitry having an input which is electrically coupled to the bit line may receive a signal which is responsive to the current conducted on the bit line, and, in response thereto, to (i) sense the data state stored in the selected memory cell and (ii) output a signal which is representative thereof.
• the integrated circuit device may also include current regulation circuitry, electrically coupled to the bit line, to sink or source at least a portion of the current conducted on the bit line by the selected memory cell during only a portion of the read operation.
• Sensing circuitry coupled between the bit line and the current regulation circuitry, may responsively couple the current regulation circuitry to the bit line during the portion of the read operation.
• the sensing circuitry includes a transistor (for example, a p-channel or n-channel type transistor) wherein the transistor provides a current path between the bit line and the current regulation circuitry in response to a predetermined voltage on the bit line.
• the sensing circuitry includes a switch which provides a current path between the bit line and the current regulation circuitry in response to a predetermined voltage on the bit line.
• the sense amplifier circuitry may sense the data state of the selected memory cell using an amplitude of the voltage on the bit line.
• the amplitude of the voltage on the bit line is responsive to the amount of current on the bit line conducted by the electrically floating body transistor associated with the selected memory cell during the read operation.
• the current regulation circuitry includes a current mirror circuit.
• the present inventions are directed to an integrated circuit device comprising a memory cell array including: (a) a plurality of memory cells wherein each memory cell includes an electrically floating body transistor including a body region which is electrically floating, wherein each memory cell is programmable to store one of a plurality of data states including (i) a first data state representative of a first charge in the body region of the transistor, and (ii) a second data state representative of a second charge in the body region of the transistor, and (b) a bit line having an intrinsic capacitance, wherein a plurality of the memory cells are coupled to the bit line.
• the integrated circuit according to this aspect of the present inventions includes:
• the present inventions are directed to a method of reading a memory cell which is disposed on integrated circuit device comprising a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, wherein the memory cell array includes a plurality of memory cells wherein each memory cell includes an electrically floating body transistor including a body region which is electrically floating, wherein each memory cell is programmable to store one of a plurality of data states including (i) a first data state representative of a first charge in the body region of the transistor, and (ii) a second data state representative of a second charge in the body region of the transistor.
• the method according to this aspect of the inventions comprises
• the method may further include sensing a predetermined voltage on the bit line, wherein sinking or sourcing at least a portion of the current conducted on the bit line further includes sinking or sourcing a substantial portion of the current provided on the bit line by the electrically floating body transistor after sensing the predetermined voltage on the bit line.
• the method may further include providing a current path during only a portion of the read operation in order to sink or source at least a portion of the current provided on the bit line by the electrically floating body transistor of the selected memory cell.
• determining the data state stored in the selected memory cell using the signal which is responsive to the current conducted by the electrically floating body transistor may further includes using an amplitude of the voltage on the bit line to determine the data state stored in the selected memory cell.
• the amplitude of the voltage on the bit line may be responsive to the amount of current conducted on the bit line during the read operation.
• FIG. 1 is a schematic block diagram illustration of a conventional memory cell array having a plurality of memory cells arranged in an array of a plurality of rows and columns, in conjunction with row and column address decoders, word line drivers and data read/write circuitry;
• FIG. 2A is a schematic representation of a portion of a prior art memory cell array including a plurality of memory cells wherein each memory cell includes one electrically floating body transistor;
• FIG. 2B is a three dimensional view of an exemplary prior art memory cell comprised of one electrically floating body transistor (PD-SOI NMOS);
• PD-SOI NMOS electrically floating body transistor
• FIG. 2C is a cross-sectional view of the memory cell of FIG. 2B , cross-sectioned along line C-C′;
• FIG. 2D is a plan view layout (not drawn to scale) of a portion of the memory cell array of FIG. 2A ;
• FIGS. 3A and 3B are exemplary schematic illustrations of the charge relationship, for a given data state, of a prior art memory cell comprised of an electrically floating body transistor (N-channel type transistor);
• FIGS. 4A-4D are schematic block diagram illustrations of exemplary read circuitry, according to certain aspects and/or embodiments of the present inventions, wherein FIGS. 4A and 4C illustrate exemplary embodiments of read circuitry in conjunction with generic memory cells and the memory cell array including a plurality of such memory cells, and FIGS. 4B and 4D illustrate exemplary embodiments of read circuitry in conjunction with a specific memory cell which includes an electrically floating body transistor (wherein the data state is stored in the electrically floating body region) and the memory cell array including a plurality of such memory cells;
• FIGS. 5A and 5B are schematic block diagram illustrations of exemplary sense amplifier circuitry of FIGS. 4A-4D , according to certain aspects and/or embodiments of the present inventions;
• FIGS. 6A and 6B are schematic block diagram illustrations of exemplary current regulation circuitry of FIGS. 4A-4D , according to certain aspects and/or embodiments of the present inventions;
• FIGS. 7A-7D are schematic block diagram illustrations of exemplary sensing circuitry of FIGS. 4A-4D , according to certain aspects and/or embodiments of the present inventions;
• FIGS. 8A and 8B are schematic illustrations of exemplary bit line precharge circuitry of FIGS. 4C and 4D , according to certain aspects and/or embodiments of the present inventions;
• FIG. 9 is a block diagram illustration of exemplary reference voltage generation circuitry to generate one or more reference voltages, according to certain aspects and/or embodiments of the present inventions.
• FIG. 10A illustrates an exemplary timing relationship of selected control signals, the amplitude of the voltage applied to an input of the sense amplifier circuitry (V bitline ), and the output of the sense amplifier circuitry in response to reading, sensing, detecting, sampling and/or determining a logic level high data state stored in the selected memory cell read information coupled to a bit line, according to certain aspects and/or embodiments of the present inventions;
• FIG. 10B illustrate exemplary relationships of the amplitude of the current (I bitcell ) output by a memory cell having a logic level high data state stored therein in relation to (a) the amplitude of the voltage (V bitline ) developed and/or formed on the bit line in response thereto and (b) the amplitude of the current (I reg — cir ) which is sunk by the current regulation circuitry, according to certain aspects and/or embodiments of the present inventions;
• FIG. 10C illustrate exemplary relationships of the amplitude of the current on the bit line (I bitline ) as a function of or in relation to the amplitude of the voltage (V bitline ) developed and/or formed on the bit line in response thereto, wherein after the current regulation circuitry is connected to the bit line (via the sensing circuitry) the current on the bit line (I bitline ) may be characterized as the difference of the current (I bitcell ) output by a memory cell having a logic level high data state stored therein and the current (I reg — cir ) which is sunk by the current regulation circuitry, according to certain aspects and/or embodiments of the present inventions;
• FIGS. 11A-11C are schematic block diagram illustrations of exemplary integrated circuit devices in which the sense amplifier circuitry and/or architecture may be implemented, wherein FIGS. 11A and 11C are logic devices (having logic circuitry and resident memory) and FIG. 11B is a memory device (having primarily function of memory), according to certain aspects of the present inventions;
• FIGS. 12A and 12B are schematic block diagram illustrations of a portion of an exemplary memory cell array architecture (as described and illustrated in U.S. Patent Application Publication No. 2007/0241405, by Popoff, (“Semiconductor Memory Array Architecture, and Method of Controlling Same”) in conjunction with sense amplifier circuitry, wherein the adjacent bit lines are connected to different sense amplifier circuitry; and
• FIG. 13 is a schematic block diagram illustration of an exemplary embodiment of the bit line selection circuit, in conjunction with read circuitry of the present inventions, and certain peripheral circuitry (i.e., reference generation circuitry and memory cell selection circuitry); and
• FIGS. 14A and 14B are schematic block diagram illustrations of exemplary read circuitry, according to certain aspects and/or embodiments of the present inventions, wherein the memory cell array may include generic memory cells and/or specific memory cells which includes an electrically floating body transistor (wherein the data state is stored in the electrically floating body region) and the memory cell array including a plurality of such memory cells.
• the memory cell array may include generic memory cells and/or specific memory cells which includes an electrically floating body transistor (wherein the data state is stored in the electrically floating body region) and the memory cell array including a plurality of such memory cells.
• the present inventions are directed to an integrated circuit device having read circuitry and/or read circuitry architectures for use with a memory cell array having a plurality of memory cells arranged, for example, in a matrix of rows and columns.
• the present inventions are directed to methods of reading and/or operating the memory cells of the memory cell array using, for example, the read circuitry of the present inventions.
• the memory cell array and read circuitry and/or architectures may comprise a portion of the integrated circuit device, for example, a logic device (such as, a microcontroller, microprocessor or the like) or a memory device (such as, a discrete memory device).
• the present inventions may be implemented in conjunction with any memory cell technology, whether now known or later developed.
• the memory cells may include one or more transistors having electrically floating body regions, one or more transistors wherein each transistor includes a plurality of electrically floating gates, junction field effect transistors (often referred to as JFETs), thyristor-based memory cells or any other memory/transistor technology whether now known or later developed. All such memory technologies are intended to fall within the scope of the present inventions.
• the present inventions may be implemented in conjunction with any type of memory type (whether discrete or integrated with logic devices).
• the memory may be a DRAM, SRAM and/or Flash. All such memories are intended to fall within the scope of the present inventions.
• the memory cells of the memory cell array may include at least one transistor having an electrically floating body transistor which stores an electrical charge in the electrically floating body region thereof.
• the amount of charge stored in the in the electrically floating body region correlates to the data state of the memory cell.
• One type of such memory cell is based on, among other things, a floating body effect of semiconductor on insulator (SOI) transistors.
• SOI semiconductor on insulator
• the memory cell may consist of a partially depleted (PD) or a fully depleted (FD) SOI transistor or bulk transistor (transistor which formed in or on a bulk material/substrate) having a gate, which is disposed adjacent to the electrically floating body and separated therefrom by a gate dielectric.
• the body region of the transistor is electrically floating in view of the insulation or non-conductive region, for example, in bulk-type material/substrate, disposed beneath the body region.
• the state of memory cell may be determined by the concentration or amount of charge contained or stored in the body region of the SOI or bulk transistor which may determine the amount of current output or conducted in response to the application of read control signals.
• read circuitry 100 may include sense amplifier circuitry 102 , current regulation circuitry 104 and sensing circuitry 106 .
• the present inventions are implemented in conjunction with a “generic” memory cell technology. (See, for example, FIG. 4A wherein read circuitry 100 is illustrated in conjunction with any type of memory cell and a memory cell array including a plurality of such memory cells).
• the present inventions are implemented in conjunction with a memory cell array 10 having a plurality of memory cells 12 including at least one electrically floating body transistor 14 . (See, for example, FIG. 4B ).
• sense amplifier circuitry 102 reads, senses, samples, detects and/or determines the data state stored in the memory cell.
• sense amplifier circuitry 102 (for example, a cross-coupled sense amplifier or a comparator) is coupled to the bit line, at given or predetermined time in the read operation, to receive a signal which is representative of the data state stored in the memory cell (for example, V bitline ).
• the sense amplifier circuitry 102 may employ sensing circuitry and/or techniques. In the context of a voltage sense amplifier, sense amplifier circuitry 102 may, in response to a control signal, compare a signal which is representative of the data state of the memory cell to a reference signal, for example, a voltage of a reference cell or output of reference generation circuitry. (See, for example, FIGS. 5A and 5B ). From that comparison, sense amplifier circuitry 102 determines the data state stored in the memory cell.
• a reference signal for example, a voltage of a reference cell or output of reference generation circuitry.
• the sense amplifier circuitry 102 may be any circuitry and employ any technique, whether now known or later developed, which reads, senses, samples, detects and/or determines the data state stored in the memory cell.
• sense amplifier circuitry 102 may include the circuitry described and illustrated in U.S. Pat. No. 7,301,838.
• the sense amplifier include the sense amplifier circuitry described and illustrated in U.S. Provisional Patent Application Ser. No. 60/967,605 (Inventor: Philippe Graber, Filed: Sep. 6, 2007, Title: “Sense Amplifier Circuitry for Integrated Circuit Having Memory Cell Array, and Method of Operating Same”).
• sense amplifier circuitry 102 may couple to one of the regions of transistor 14 (for example, drain region 22 ) of memory cell 12 to read, sense, sample, detect and/or determine the data state stored in memory cell 12 based on or based substantially on the current output or conducted by transistor 14 (i.e., I bitcell ) of memory cell 12 .
• sense amplifier circuitry 102 reads, senses, samples, detects and/or determines the data state stored in memory cell 12 based on or based substantially on a bipolar transistor current (or a signal which is representative thereof) output and/or conducted by transistor 14 (via the intrinsic bipolar transistor), as described in, for example, U.S. Pat. No.
• sense amplifier circuitry 102 reads, senses, samples, detects and/or determines the data state stored in memory cell 12 based on or based substantially on a channel current (or a signal which is representative thereof) output and/or conducted by transistor 14 , as described in, for example, U.S. Pat. No. 6,969,662.
• the current output and/or conducted by transistor 14 (whether bipolar, channel or a combination thereof) is based on (or substantially based on) the relative amount of majority carriers stored, contained or resident in electrically floating body region 18 of transistor 14 of memory cell 12 (relatively more majority carries 34 contained within body region 18 may be representative of a logic high data state and a relatively less majority carries 28 contained within body region 18 may be representative of a logic low data state).
• read circuitry 100 further includes current regulation circuitry 104 to regulate and/or control the amount of current which flows through the memory cell during the read operation (in those instances where the selected memory cell stores a logic high data state).
• current regulation circuitry 104 to regulate and/or control the amount of current which flows through the memory cell during the read operation (in those instances where the selected memory cell stores a logic high data state).
• the current i.e., I bitcell
• the memory cell for example, by transistor 14 of memory cell 12 illustrated in FIG. 4B
• the current is provided to node 108 .
• I bitcell a portion or all of the current (i.e., I bitcell ) charges the intrinsic capacitance of the bit line, which is represented by capacitor 110 (C bitline ).
• V bitline the amplitude of the voltage on the bit line
• I bitcell a portion of the current output or conducted by the memory cell (i.e., I bitcell ) is provided to current regulation circuitry 104 (i.e., I reg — cir ).
• the charge integrated and/or stored by the intrinsic capacitance of the bit line provides a voltage V bitline which, in one example, is employed by sense amplifier circuitry 102 to read, sense, sample, detect and/or determine the data state stored in memory cell coupled to the bit line (for example, memory cell 12 coupled to bit line 32 in FIG. 4B ).
• a voltage signal is employed to determine the state of the memory cell and that voltage is generated by storing or integrating (on or by bitline capacitor 110 ) the current output or conducted by memory cell 12 during a certain time interval.
• regulating the current output or conducted by transistor 14 of memory cell 12 may provide an advantage during operation of memory cells 12 in memory cell array 10 . (See, for example, FIG. 4B ).
• voltage across the memory cell 12 self adjusts to sustain current imposed by current regulation circuitry 104 .
• the voltage levels applied to the gate of transistor 14 for reading and writing may be the same or substantially the same.
• transistor 14 of memory cell 12 may be configured in the same or similar condition at the conclusion of a read operation (where memory cell 12 stores a logic high data state) and write operation (where a logic high data state is written into or stored in memory cell 12 ).
• Such a situation may be advantageous where the memory cell array is configured in particular architectures where the level of charge stored in memory cells programmed to a logic high state has to be well controlled such that little to no disturbance may be observed in memory cells adjacent to a selected memory cell (which stores a logic high data state).
• the operation and response of memory cells 12 may be more reliable and the peripheral control circuitry and control techniques (for example, the word line drivers and data read/write circuitry—see, for example, FIG. 1 ) may be simplified.
• the current regulation circuitry 104 may be any circuitry, whether now known or later developed, which controls the amount of an input or output current.
• current regulation circuitry 104 may be implemented using a current mirror circuit. (See, for example, FIG. 6A ). In the illustrative embodiment of FIG. 6A , current regulation circuitry 104 will seek to sink an input current (I reg — cir ) which is equal to an amount of current I reg — max .
• current regulation circuitry 104 may be implemented via other circuitry and/or techniques; all such circuitry and/or techniques, whether now known or later developed, are intended to fall within the scope of the present inventions.
• the current source may include two transistors (in one exemplary embodiment, two P-channel type transistors). The two transistors, in combination, generate (or attempt to generate) a relatively stable constant current.
• the current (I reg — max ) provided by the current source depends on the distribution, range and/or anticipated of the output current of the memory cell (among other things), in one exemplary embodiment, the current I reg — max may be 5 ⁇ A under those circumstances where output current of transistor 14 of memory cell 12 is expected to be 30 ⁇ A when a logic high data state is stored therein and read therefrom.
• current source may be any circuit or device, whether now known or later developed, which generate and output a relatively stable constant current.
• read circuitry 100 further includes sensing circuitry 106 , disposed between node 108 and the input of current regulation circuitry 104 .
• sensing circuitry 106 responsively couples node 108 (or provides a current path from node 108 ) to current regulation circuitry 104 .
• sensing circuitry 106 couples node 108 (or provides a current path from node 108 ) to current regulation circuitry 104 so that, thereafter, a portion (or all) of the current output or conducted by the memory cell (i.e., I bitline ) is provided to or sunk by current regulation circuitry 104 .
• sensing circuitry 106 in conjunction with current regulation circuitry 104 , controls and/or regulates the amount of current available from or provided by the memory cell (i.e., I bitline ) to charge the intrinsic capacitance (capacitor 110 (C bitline )) of the bit line and/or form, provide or establish a voltage at node 108 .
• sense amplifier circuitry 102 may read, sense, sample, detect and/or determine a logic high data state stored in the memory cell—regardless of the different output or response characteristics and/or distributions of the memory cells of the memory cell array.
• the amplitude of the input signal of sense amplifier circuitry 102 (which is used to read, sense, sample, detect and/or determine a logic high data state stored in the memory cell) may be limited or restricted (the distribution thereof relatively more narrow) notwithstanding the distribution of different output or response characteristics of the memory cells of the memory cell array.
• the sensing circuitry 106 may be any circuitry and employ any technique, whether now known or later developed, which (1) senses, detects and/or determines a predetermined amount of current to the intrinsic capacitance (capacitor 110 (C bitline )) of the bit line and/or a predetermined voltage at node 108 , and (2) electrically couples node 108 (or provides a current path from node 108 ) to current regulation circuitry 104 .
• sensing circuitry 106 may be implemented using comparator circuitry 112 to sense, detect and/or determine the amount of charge or current by memory cell (i.e., I bitline ) and/or (ii) amplitude of the voltage at node 108 . (See, for example, FIGS.
• comparator when the voltage on signal line 106 a is equal to or exceeds a predetermined or threshold voltage (V threshold ), comparator enables the switch 114 a or transistor 114 b to connect current regulation circuitry 104 to node 108 and thereafter allow current (I reg — cir ) to flow to current regulation circuitry 104 which sinks some or all of the current output from or conducted by the memory cell (I bitline ).
• V threshold a predetermined or threshold voltage
• the amplitude or level of the threshold voltage (V threshold ) is less than the bit line voltage quiescent point.
• the threshold voltage (V threshold ) may be 0.1V.
• sensing circuitry 106 may be implemented using p-channel transistor 114 c or n-channel transistor 114 d , respectively, having a predetermined reference voltage applied the gate thereof.
• transistor 114 c in operation, when the voltage on signal line 106 a is equal to or exceeds a threshold voltage (of transistor 114 c ) greater than reference voltage Vref 1 , transistor 114 c “turns on” and provides a current path from node 108 to current regulation circuitry 104 (which allows current regulation circuitry 104 to sink some or all of the current output or conducted from the memory cell (I bitcell )).
• the reference voltage Vref 1 is equal to or substantially equal to ground or common.
• the amplitude of the voltage necessary to “turn on” transistor 114 b is equal to the amplitude or level of the threshold voltage (V threshold ) discussed above in connection with the embodiments of FIGS. 7A and 7B .
• transistor 114 c and 114 d may start to conduct current before the voltage on signal line 106 a is equal to or exceeds a threshold voltage (i) higher than reference voltage Vref 1 for transistor 114 c or (ii) lower for transistor 114 d than reference voltage Vref 1 .
• transistor 114 c or transistor 114 d may be sized, designed and/or fabricated to provide predetermined temporal response characteristics as well as input/output characteristics. For example, the level of body implant may be adjusted to provide adequate control for the conduction threshold of transistor 114 c or transistor 114 d.
• sensing circuitry 106 may be any circuitry and employ any technique, whether now known or later developed, which senses, detects and/or determines a predetermined voltage on the intrinsic capacitance (capacitor 110 (C bitline )) of the bit line and/or a predetermined voltage at node 108 , and, in response thereto, electrically couples node 108 (or provides a current path from node 108 ) to current regulation circuitry 104 .
• read circuitry 100 may further include bit line precharge circuitry 116 .
• bit line precharge circuitry 116 is connected to the bit line, via signal line 116 a , to establish or provide a predetermined condition or state thereon (for example, a predetermined voltage amplitude) at the start of or immediately prior to reading the data state of the memory cell.
• the bit line precharge circuitry 116 may be any circuitry, whether now known or later developed, which establishes or provides a predetermined condition on the bit line at the start of or prior to reading the data state of the memory cell.
• bit line precharge circuitry 116 may include transistor 118 which is controlled via a precharge control signal coupled to the gate thereof.
• Vref 2 may be a voltage that is equal to or substantially equal to ground or common.
• the integrated circuit may include reference generation circuitry 120 to generate or provide one, some or all of the reference voltages and/or reference currents employed herein. Such circuitry is well known to those skilled in the art.
• read circuitry 100 includes (i) a precharge phase, condition or state wherein certain portions and/or nodes of read circuitry 100 are placed in a predetermined state and (ii) a data sense and sample phase, condition or state wherein the memory cell provides information (for example, a current and/or voltage signal) on the bit line which is read, sensed, sampled, detected and/or determined by sense amplifier circuitry 102 .
• the precharge control signal is asserted and the bit line is coupled to a reference voltage which, in this embodiment, is ground or common.
• the selection signal(s) is/are applied to the memory cell to select and couple a particular memory cell to the bit line.
• a suitable memory cell selection signal V WLRD
• a second temporally varying memory cell selection signal may be applied to the source region of transistor 14 via source line 30 .
• the data sense and sample phase of the read operation commences immediately after the precharge control signal is deasserted and transistor 118 is disabled.
• the amplitude of the voltage on bit line 32 is “permitted” to increase in response to a current (I bitline ) which flows on bit line 32 from the selected memory cell 12 (in response to suitable control signals applied to gate of transistor 14 , via word line 28 , and/or the source region of transistor 14 , via source line 30 ).
• sense amplifier circuitry 102 employs the sense amplifier circuitry described and illustrated in U.S. Provisional Patent Application Ser. No. 60/967,605 (Inventor: Philippe Graber, Filed: Sep. 6, 2007, Title: “Sense Amplifier Circuitry for Integrated Circuit Having Memory Cell Array, and Method of Operating Same”)
• the various nodes and/or elements of read circuitry 100 and, in particular, various nodes and elements of the particular sense amplifier circuitry may undergo “settling” before implementation of a read operation.
• optimum, (highly) predetermined, suitable and/or proper conditions may exist which facilitates highly reliable and/or highly repetitive reading, sensing, and/or sampling of the information on bit line.
• transistor 114 c When the amplitude of the voltage on the bit line is equal to or exceeds a threshold voltage (V threshold ) of transistor 114 c (in this exemplary embodiment, reference voltage Vref 1 is ground or 0 volts), transistor 114 c “turns on” and the current regulation circuitry 104 may draw or sink bit line current (I bitline ) via the current path provided by the sensing circuitry 106 . Under these circumstances, current regulation circuitry 104 sinks some or all of the current output or conducted by the memory cell (I bitline ). Moreover, via connection of current regulation circuitry 104 to the bitline, the rise time of the amplitude of the voltage on the bit line (V bitline ) is controlled by diversion of current to current regulation circuitry 104 . (See, for example, FIGS. 10B and 10C ).
• sense amplifier circuitry 102 reads, senses, samples, detects and/or determines the voltage on the bit line (which is representative of the logic high data state stored in the selected memory cell) via asserting the control signal, “Sample”. In response thereto, sense amplifier circuitry 102 outputs a signal which is representative of the logic high data state stored in the selected memory cell. (See, FIG. 10A ).
• the present inventions may provide a more desired and/or suitable control of the current regulation technique by limiting and/or controlling the timing of when the regulation circuitry 104 draws or sinks bit line current (I bitline ). That is, in contrast to conventional current regulation technique and/or architectures, the present inventions prevent or inhibit current regulation circuitry 104 from drawing or sinking current from the bitline (and the bitline capacitance) until a predetermined condition exists or is sensed on the bitline and/or until a predetermined time of/in the read operation. For example, in the embodiment of FIG.
• sensing circuitry 106 before sensing circuitry 106 detects the bit line voltage (V bitline ) is equal to or exceeds a threshold voltage (of transistor 114 c ) greater than reference voltage Vref 1 , current regulation circuitry 104 is electrically decoupled from the bit line and, as such, the voltage on the bit line (V bitline ) rapidly increases via charge accumulation on the intrinsic capacitance 110 of the bit line (C bitline ).
• sensing circuitry 106 electrically couples current regulation circuitry 104 to the bit line, which allows current regulation circuitry 104 to sink some or all of the current output from or conducted by the memory cell (I bitline )).
• the rise time (t rise ) of the amplitude of the voltage on the bit line (V bitline ) is increased (relative to conventional current regulation techniques/architectures) and the detection threshold (V sample — ref ) of sense amplifier circuitry 102 is attained and exceeded earlier (relative to conventional current regulation techniques/architectures).
• the selected memory cell in the event that the selected memory cell stores a logic low data state, the selected memory cell provides or conducts little to no current (I bitline ) (or an insufficient amount of current (I bitline )) on the bit line.
• the voltage on the bit line (V bitline ) does not sufficiently increase to “turn on” transistor 114 c and, as such, sensing circuitry 106 does not couple current regulation circuitry 104 to node 108 to allow circuitry 104 to sink or draw some or all of the bit line current (I bitline ).
• sense amplifier circuitry 102 responsively reads, senses, samples, detects and/or determines a logic low data state, as well as outputs data which is representative of that logic low data state.
• read circuitry 100 does not include bit line precharge circuitry 116
• the operation is similar to that discussed above except that the read operation does not include a precharge phase.
• the data sense and sample phase of the read operation wherein the memory cell provides information (for example, a current and/or voltage signal) on the bit line which is read, sensed, sampled, detected and/or determined by sense amplifier circuitry 102 .
• the integrated circuit of the present inventions further includes memory cell selection and control circuitry.
• memory cell selection and control circuitry selects or enables one or more memory cells (for example, memory cells 12 of FIGS. 4B and 4D ) to facilitate reading data therefrom and/or writing data thereto by, depending on the type of memory cell, applying one or more control signals on one or more word lines and/or control lines (see, FIGS. 4A and 4C ) and/or applying one or more control signals on one or more word lines and/or source lines (see, FIGS. 4B and 4D ).
• the memory cell selection and control circuitry may generate such control signals using address data, for example, row address data.
• memory cell selection and control circuitry may include a conventional word line decoders, source line decoders, word line drivers and/or source line drivers.
• control/selection techniques and circuitry therefor to implement the memory cell selection technique. All such control/selection techniques, and circuitry therefor, whether now known or later developed, are intended to fall within the scope of the present inventions including those incorporated by reference herein (as discussed above).
• the present inventions may be implemented in an integrated circuit that is a logic device which includes a memory portion and logic portion (see, for example, FIGS. 11A and 11C ), or an integrated circuit that is primarily a memory device (see, for example, FIG. 11B ).
• the logic device may be, for example, a processor, controller, field programmable gate array, state machine, and/or a device including same.
• the present inventions may be implemented in any device employing a memory array and read circuitry.
• the present inventions may be employed in conjunction with any memory cell technology now known or later developed.
• the present inventions may be implemented in conjunction with a memory array, having a plurality of memory cells each including an electrically floating body transistor.
• a memory array having a plurality of memory cells each including an electrically floating body transistor.
• the memory cell may consist of a PD or a FD SOI or transistor (or transistor formed on or in bulk material/substrate) having a gate, which is disposed adjacent to the electrically floating body and separated therefrom by a gate dielectric.
• the body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region.
• the state of memory cell is determined by the concentration of charge within the body region of the SOI transistor. The entire contents of these U.S.
• the memory cells of the memory cell array may be comprised of N-channel, P-channel and/or both types of transistors.
• circuitry that is peripheral to the memory array for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated in detail herein)
• N-channel type transistors or P-channel type transistors are employed as memory cells in the memory array(s)
• suitable write and read voltages are well known to those skilled in the art (and in view of the U.S. Patents and U.S. Patent Applications incorporated herein by reference).
• the present inventions may be implemented in conjunction with any memory cell array configuration and/or arrangement of the memory cell array.
• integrated circuit device for example, memory or logic device
• integrated circuit device may include a plurality of memory cell arrays, each having a plurality of memory cells, wherein the read circuitry of the present invention may be shared between a plurality of memory cell arrays or dedicated to one memory cell array.
• the present inventions may be employed in any architecture or layout and/or technique of sensing data from memory cells of a memory cell array.
• read circuitry 100 may be employed in the architectures, circuitry and techniques described and illustrated in U.S. Patent Application Publication No.
• reading and programming circuitry includes read circuitry 100 a which may be selectively coupled to bit lines 32 a and 32 c , and read circuitry 100 b coupled to bit lines 32 b and 32 d .
• one of the bit lines i.e., the active bit line
• the data sense circuitry is selectively connected to the data sense circuitry in order to sense the data state stored in a memory cell and/or write a data state into a memory cell which is associated with the selected bit line.
• the bit lines 32 a and 32 c is connected to read circuitry 100 a .
• one of the bit lines 32 b and 32 d is connected to read circuitry 100 b.
• the active bit line is selected by memory cell selection circuitry using, for example, one or more bits of the row address (for example, the MSB or LSB).
• the other bit line is disconnected from the read circuitry 100 .
• the memory cells may be arranged, configured and/or controlled using any of the memory cell arrays, architectures and/or control/operation techniques.
• the memory cells may be arranged, configured and/or controlled using any of the memory cell arrays, architectures and/or control/operation techniques described and illustrated in the following U.S. Patent Applications:
• the present inventions may be fabricated using well known techniques and/or materials. Indeed, any fabrication technique and/or material, whether now known or later developed, may be employed to fabricate the memory cells, transistors and/or memory array(s).
• the present inventions may employ silicon (whether bulk-type or SOI), germanium, silicon/germanium, gallium arsenide or any other semiconductor material in which transistors may be formed.
• the electrically floating body transistors, memory cells, and/or memory array(s) may employ the techniques described and illustrated in U.S. Pat. No. 7,335,934, by Fazan, (“Integrated Circuit Device, and Method of Fabricating Same”) and/or U.S. Patent Application Publication No.
• Integrated Circuit Device Patent Applications 2007/0085140, by Bassin, (“One Transistor Memory Cell having a Strained Electrically Floating Body Region, and Method of Operating Same”) (hereinafter collectively “Integrated Circuit Device Patent Applications”).
• Integrated Circuit Device Patent Applications The entire contents of the Integrated Circuit Device Patent Applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein.
• an integrated circuit device includes memory section (having a plurality of memory cells, for example, PD or FD SOI memory transistors) and logic section (having, for example, high performance transistors, such as FinFET, multiple gate transistors, and/or non-high performance transistors (for example, single gate transistors that do not possess the performance characteristics of high performance transistors)).
• memory section having a plurality of memory cells, for example, PD or FD SOI memory transistors
• logic section having, for example, high performance transistors, such as FinFET, multiple gate transistors, and/or non-high performance transistors (for example, single gate transistors that do not possess the performance characteristics of high performance transistors)).
• the memory cell and/or memory cell array, as well as the circuitry of the present inventions may be implemented in an integrated circuit device having a memory portion and a logic portion (see, for example, FIGS. 11A and 11C ), or an integrated circuit device that is primarily a memory device (see, for example, FIG. 11B ).
• the memory array may include a plurality of memory cells arranged in a plurality of rows and columns wherein each memory cell includes a transistor (whether fabricated in a bulk-type material or SOI material), for example, an electrically floating body transistor.
• the memory arrays may be comprised of N-channel, P-channel and/or both types of transistors.
• circuitry that is peripheral to the memory array for example, data sense circuitry (for example, sense amplifiers or comparators), memory cell selection and control circuitry (for example, word line and/or source line drivers), as well as row and column address decoders) may include P-channel and/or N-channel type transistors.
• the read circuitry may be implemented in conjunction with one or more circuits (for example, one or more drivers, inverters and/or latches) to, for example, more fully establish, obtain/provide a predetermined or proper polarity of, and/or maintain the data read, sensed, sampled and/or determined by sense amplifier circuitry 102 during the read/data sense operation and output on signal line 102 b .
• one or more circuits for example, one or more drivers, inverters and/or latches
• read circuitry of the present inventions may employ any of the configurations of the sense amplifier circuitry, sensing circuitry, current regulation circuitry and bit line precharge circuitry described, incorporated by reference and/or illustrated herein. All permutations and combinations of configurations for read circuitry are intended to fall within the scope of the present inventions. Moreover, all permutations and combinations of configurations of the read circuitry may be implemented in conjunction with any of the memory cells, memory cell technologies, memory cell array architectures and memory types described, incorporated by reference and/or illustrated herein. For the sake of brevity all permutations and combinations will not be discussed in detail but are intended to fall within the scope of the present inventions.
• each of the aspects of the present inventions, and/or embodiments thereof may be employed alone or in combination with one or more of such aspects and/or embodiments.
• those permutations and combinations will not be discussed separately herein.
• the present inventions are neither limited to any single aspect (nor embodiment thereof), nor to any combinations and/or permutations of such aspects and/or embodiments.
• the present inventions prevent or inhibit current regulation circuitry 104 from providing or sourcing current to the bit line (and the bit line capacitance) until sensing circuitry 106 senses, detects and/or determines a predetermined condition exists or is sensed on the bit line and/or until a predetermined time of/in the read operation. (See, for example, FIGS.
• transistor 114 d turns “on” upon sensing, detecting and/or determining a predetermined condition exists or is sensed on the bit line (for example, the amplitude of the bit line voltage falls one threshold voltage below the reference voltage of Vref 1 ).
• current regulation circuitry 104 draws or sinks current during the read operation or (ii) current regulation circuitry 104 provides or sources current during the read operation.
• exemplary read circuitry 100 of the embodiment of FIGS. 14A and 14B is similar to that described above with respect to, for example, the embodiments of FIGS. 4A-4D except current regulation circuitry 104 provides or sources current during the read operation rather than draws or sinks current during the read operation (as discussed above).
• the current conducted by the memory cell i.e., I bitcell
• the selected memory cell stores a predetermined logic state (for example, a high data state)
• a portion or all of the current i.e., I bitcell
• V bitline a portion of the current conducted by the memory cell (i.e., I bitcell ) is sourced or provided by current regulation circuitry 104 (i.e., I reg — cir ).
• the sense amplifier 102 employs the voltage on signal line 102 a (V bitline ) to read, sense, sample, detect and/or determine the data state stored in memory cell coupled to the bit line (for example, memory cell 12 coupled to bit line 32 ).
• a voltage signal is employed to determine the state of the memory cell.
• the selected memory cell In the event that the selected memory cell stores a different logic state (for example, a logic low data state), the selected memory cell conducts little to no current (I bitcell ) (or an insufficient amount of current (I bitcell )) from the bit line.
• the voltage on the bit line (V bitline ) does not sufficiently decrease to “turn on” transistor 114 c and, as such, sensing circuitry 106 does not couple current regulation circuitry 104 to node 108 to allow circuitry 104 to source or provide some or all of the bit line current (I bitcell ).
• the amplitude of the voltage on the bit line does not decrease below the reference voltage level (V sample — ref ) applied to sense amplifier circuitry 102 and/or a quiescent level (V quiescent ).
• sense amplifier circuitry 102 responsively reads, senses, samples, detects and/or determines, in this example, a logic low data state, as well as outputs data which is representative of that logic low data state.
• sensing circuitry 106 may include or employ any of the embodiments described and illustrated herein.
• DC reference signals for example, ground or supply
• the reference potential may be AC and/or DC signals.
• circuit may mean, among other things, a single component (for example, electrical/electronic) or a multiplicity of components (whether in integrated circuit form or otherwise), which are active and/or passive, and which are coupled together to provide or perform a desired function.
• circuitry may mean, among other things, a circuit (whether integrated or otherwise), a group of such circuits, one or more processors, one or more state machines, one or more processors implementing software, or a combination of one or more circuits (whether integrated or otherwise), one or more state machines, one or more processors, and/or one or more processors implementing software.
• data may mean, among other things, a current or voltage signal(s) whether in an analog or a digital form.
• to sense a/the data state stored in memory cell means, among other things, to sample, to sense, to read and/or to determine a/the data state stored in memory cell; “sensing a/the data state stored in memory cell”, “sensed a/the data state stored in memory cell” or the like shall have the same meaning.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Semiconductor Memories (AREA)

Abstract

Description

Claims (24)

Priority Applications (2)

Applications Claiming Priority (1)

Related Child Applications (1)

Publications (2)

Family

ID=41133115

Family Applications (2)

Family Applications After (1)

Country Status (1)

Cited By (144)

Families Citing this family (3)

Citations (298)

Family Cites Families (8)

• 2008
  • 2008-04-04 US US12/080,642 patent/US7957206B2/en active Active
• 2011
  • 2011-05-20 US US13/112,526 patent/US8274849B2/en active Active

Patent Citations (371)