US8607086B2 - Massively multicore processor and operating system to manage strands in hardware - Google Patents

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Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F9/5061—Partitioning or combining of resources
  • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• the application generally relates to computing devices having multiple processors and, more specifically, to a multicore processor and operating system based on a protocol stack.
• Computing devices such as desktop computers, laptop computers, cell phones, smartphones, personal digital assistants (PDA), and many other electronic devices are widely deployed.
• the primary element of such computing devices is a central processing unit (CPU), or a processor, which is responsible for executing instructions of one or more computer programs.
• the CPU executes each program instruction in sequence to perform the basic arithmetical, logical, and input/output operations of the computing device.
• Design and implementation of such devices in general, and CPUs in particular, may vary; however, their fundamental functionalities remain very similar.
• the CPU is coupled to a memory and an Input/Output (I/O) subsystem, directly or through a bus, to perform the main functions of computing devices such as inputting and outputting data, processing data, and so forth.
• the memory may embed an operating system (OS), computer programs, applications, and so forth.
• OS operating system
• Conventional operating systems are quite similar in architecture, in that each tends to have conventional file and memory operations, storage and graphical user interface operations, and so forth.
• Architectures of conventional operating systems include a layered design, device drivers, and Application Programming Interfaces (APIs).
• a core kernel essentially has master control over all the operations of the overlying software, components, device drivers, applications, and so forth.
• operating systems implement ‘multi-tasking’ through time slicing and sequential allocation of computer resources to various threads and processes.
• a thread generally runs within a process and shares resources, e.g., memory, with other threads within the same process, whereas a process generally runs ‘self-contained’ within its own right and completely independently of any other process.
• multi-tasking when a computing device includes a single processor, the operating system instructs the processor to switch between different threads and implement them sequentially. Switching generally happens frequently enough that the user may perceive the threads (or tasks) as running simultaneously.
• multicore processors which may truly allocate multiple threads or tasks to run at the same time on different cores.
• conventional multicore processor architectures involve a small number of cores (typically 2, 4, 6, or 8 cores) due to the design limitations of traditional hardware and traditional operating systems.
• the computing device still must implement time slicing and switching between different threads on each of its cores when performing several tasks involving multithreading allocated through the cores. In other words, even conventional multicore processors cannot implement true multitasking.
• a computing device having multiple CPUs interconnected to each other.
• Each CPU embeds an operating system of an entirely new architecture.
• This operating system may be based fundamentally around an Internet stack, for example, the TCP/IP stack (instead of including a TCP/IP layer as in a conventional core operating system) and may utilize a conventional interface or similar extensions of the standard Berkeley Sockets (or WinSock) APIs.
• a computing apparatus may comprise a set of interconnected central processing units.
• Each CPU may embed an operating system (OS) comprising an operating system kernel, the operating system kernel being a state machine and comprising a protocol stack.
• OS operating system
• At least one of the CPUs may further embed executable instructions for allocating multiple strands to one or more other CPUs of the set of interconnected CPUs.
• a strand as used herein, is a hardware oriented process and is not necessarily similar to a conventional unit of processing (i.e., a thread) that can be scheduled by an operating system.
• the Internet stack is a set of communication protocols used for the Internet and other similar networks.
• the Internet stack may comprise a TCP/IP stack such that the OS kernel is a TCP/IP stack state machine with proprietary extensions that can be used to change or access internals of the TCP/IP stack state machine.
• the Internet stack may comprise a User Datagram Protocol/Internet Protocol (UDP/IP) stack such that the OS kernel is a UDP/IP stack state machine with proprietary extensions that can be used to change or access internals of the UDP/IP stack state machine.
• the CPU may comprise a processing unit, a memory and an I/O interface.
• Executable instructions for the operating system may be stored within one or more types of storage media, such as for example, Read-Only Memory (ROM), Programmable Read-Only Memory (PROM), Field Programmable Read-Only Memory (FPROM), One-Time Programmable Read-Only Memory (OTPROM), One-Time Programmable Non-Volatile Memory (OTP NVM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM or Flash ROM).
• ROM Read-Only Memory
• PROM Programmable Read-Only Memory
• FPROM Field Programmable Read-Only Memory
• OTPROM One-Time Programmable Read-Only Memory
• OTP NVM One-Time Programmable Non-Volatile Memory
• EPROM Erasable Programmable Read-Only Memory
• EEPROM or Flash ROM Electrically Erasable Programmable Read-Only Memory
• the computing apparatus may further comprise at least one asynchronous clock to serve as an internal clock for the operating system.
• the asynchronous clock may be configurable to automatically stop when clock cycles are no longer needed.
• a time reference for the operating system kernel may be based, for example, on a Network Time Protocol (NTP), Simple Network Time Protocol (SNTP), or other suitable time protocol from a remote time server.
• NTP Network Time Protocol
• SNTP Simple Network Time Protocol
• the operating system may utilize a Sockets style API of sockets and ports on IP addresses for handling I/O requests.
• the set of CPUs may be interconnected through a bus. Executable instructions for the operating system may be executed through a Sockets API.
• the at least one CPU that embeds executable instructions for allocating multiple strands may further comprise instructions for generating multiple strands.
• a method for operating a computing apparatus may comprise receiving I/O requests, generating multiple strands according to the I/O requests, allocating the multiple strands to one or more CPUs of a set of CPUs, and processing the multiple strands.
• Each CPU may embed an operating system (OS) having a kernel comprising a protocol stack.
• OS operating system
• the I/O requests may be received by a CPU, which embeds executable instructions for allocating multiple strands through multiple CPUs.
• Allocating multiple strands may comprise communicating data via a network interface.
• the method may further comprise assembling results of multiple strands processing.
• Executable instructions for the operating system may be stored in a memory and executed through a Sockets API.
• a non-transitory computer-readable storage medium having embodied instructions thereon, instructions executable by a processor in a computing device to perform a method.
• the method may comprise receiving an input/output (I/O) request, generating one or more strands according to the I/O request, allocating the one or more strands and/or processes to one or more central processing units (CPUs) of a set of CPUs, wherein each CPU of the set embeds an operating system (OS) having a kernel comprising a protocol stack, and processing the one or more strands and/or processes.
• I/O input/output
• CPUs central processing units
• OS operating system
• FIG. 1 is a block diagram of a CPU, according to various exemplary embodiments.
• FIG. 2 illustrates an exemplary architecture of an Internet stack state machine-based system, according to various embodiments.
• FIG. 3 is a flow chart illustrating a method for a CPU embedding a protocol stack-based operating system, according to an exemplary embodiment.
• FIG. 4 is a block scheme of a computing device, according to various exemplary embodiments.
• FIG. 5 is a computing environment, according to various exemplary embodiments.
• FIG. 6 is a flow chart of a method for processing I/O requests by a computing device comprising multiple CPUs with embedded Internet stack-based operating systems, according to an exemplary embodiment.
• Various embodiments disclosed herein relate to computing devices comprising a set of interconnected CPUs.
• the number of the CPUs is not limited, and may be more than 100, or even more than 10,000, depending on specific application of the computing devices.
• the CPUs may be interconnected (e.g., through one or more buses) so that multiple strands, processes, and tasks can be allocated among a few or even all CPUs, thereby implementing parallelism or true multi-tasking.
• each of some or all of the CPUs is allocated a respective strand.
• the term “central processing unit” relates to a processor, a microprocessor, a controller, a microcontroller, a chip, or other processing device that carries out arithmetic and logic instructions of an operating system, a computer program, an application, or the like.
• the CPU comprises a processing unit (typically including an arithmetic logic unit and a control unit) and a memory (also known as “registers,” or Read Only Memory (ROM)).
• the CPU may further comprise an I/O Subsystem (Interface) to allow data transfer between the CPU and any other devices such as another CPU or I/O devices such as a keyboard, mouse, printer, monitor, network controller, and so forth.
• I/O Subsystem Interface
• the CPU memory may store an operating system based entirely on a protocol stack.
• a protocol stack as used herein, is a particular software implementation of a computer networking protocol suite.
• the protocol stack may be a TCP/IP stack, UDP/IP stack, Internet Control Message Protocol (ICMP) stack, combinations thereof, or other protocols.
• ICMP Internet Control Message Protocol
• the operating system embedded in the CPU is fundamentally a state machine.
• the kernel of the operating system is fundamentally a protocol stack.
• Such an operating system is inherently Internet-oriented and all Internet type functionality is natural and inherent in its protocol stack-based processor design and implementation.
• such an operating system may operate within small hardware, be run by very compact and efficient software, possess minimal clock cycles for execution, have a natural Internet connectivity model and ultra low power consumption.
• FIG. 1 illustrates a block diagram of an exemplary CPU 100 .
• the CPU 100 may be a processor, a microprocessor, a chip, or the like.
• the CPU 100 may include a memory 110 , which may embed an operating system and, optionally, further software applications.
• the operating system may comprise a kernel to provide communications between software and hardware components/modules.
• the kernel may be a state machine with extensions and may comprise an Internet stack.
• the Internet stack may include a set of communication protocols used for the Internet and similar networks.
• the Internet stack may include a TCP/IP stack so that the OS kernel is a TCP/IP stack state machine.
• the Internet stack includes a UDP/IP stack such that the OS kernel is a UDP/IP stack state machine.
• the Internet stack includes a ICMP stack such that the OS kernel is a ICMP stack state machine.
• the memory 110 may store one or more modules. Exemplary modules, which may be stored in the memory 110 , include an I/O request receiver module 120 , a protocol handling module 130 , an I/O request processing module 140 , and an optional network interface module 150 . It will be appreciated by one skilled in the art that the technology described herein encompasses those embodiments where one or more of the modules may be combined with each other or not included in the memory 110 at all.
• the CPU 100 may further include a processing unit 160 for executing various instructions and running modules stored in the memory 110 .
• the processing unit 160 may comprise an arithmetic logic to carry out mathematical functions, and a control unit to regulate data flow through the processing unit 160 and the CPU 100 .
• Those skilled in the art would understand that any suitable architecture of the processing unit 160 is applicable.
• a module should be generally understood as one or more applications (routines) that perform various system-level functions and may be dynamically loaded and unloaded by hardware and device drivers as required.
• the modular software components described herein may also be integrated as part of an application specific component.
• the modules may each include executable instructions for the operating system embedded into CPU 100 and may be executed through a Sockets API.
• the I/O request receiver module 120 may be configured to receive I/O requests.
• the requests may be from an application residing in an application layer of a computing device (as described in further detail with respect to FIG. 2 ).
• the protocol handling module 130 may be configured to handle a specific protocol for the protocol stack state machine implementation.
• the protocol may be a TCP/IP stack such that the operating system is a TCP/IP stack state machine.
• the protocol stack may include a different protocol stack (e.g., a UDP/IP stack or ICMP stack which may be used in addition to or in place of the TCP/IP stack).
• the operating system may utilize Sockets style API of sockets and ports on IP addresses for handling I/O requests.
• the I/O request processing module 140 may be configured to process the I/O requests from an application according to the network protocol using the operating system.
• the optional network interface module 150 may be included and is configured to provide an interface between the protocol stack state machine and a network interface.
• the corresponding network interface may be a hardware unit or a “soft” Ethernet controller.
• the CPU 100 may also comprise a clock.
• the CPU 100 may require a clock to drive the state transitions as the CPU 100 , for instance, reads and decodes opcodes. Conventionally this is done by some external oscillator circuitry, typically driven by a fixed-frequency crystal. However, clocking may also be done by more than one crystal, e.g. a high frequency crystal (e.g., 50 MHz) one for the main CPU core, and other (lower frequency) crystals for other uses, e.g., programmable timers, watchdog timers etc.
• a system comprising for instance a Universal Asynchronous Receiver/Transmitter (UART) and a Network Interface Controller (NIC) also typically require clock inputs of some sort. For instance, a UART may need a reliable clock source all the way from perhaps 300 baud up to 921,600 baud. A NIC running 100 MBit Ethernet would typically need a clock source of 50 MHz or 25 MHz.
• a computer system needs to keep track of time, and can do so using internal counters to keep track of its internal clocks.
• the device is connected to the Internet and thus has readily available external time sources, for instance from Network Time Protocol (NTP), Simple Network Time Protocol (SNTP), or other suitable time protocols from a remote server (i.e., time protocol servers).
• NTP Network Time Protocol
• SNTP Simple Network Time Protocol
• time protocol servers i.e., time protocol servers
• the processing unit 160 may utilize a time reference using the NTP, SNTP, or other suitable time protocol from a remote time server.
• the Precision Time Protocol PTP
• LAN Local Area Network
• an asynchronous (variable) clock may serve as an internal clock for the operating system for the CPU 100 .
• the asynchronous clock may be configurable to automatically stop when clock cycles are no longer needed.
• the asynchronous system clock may be restarted by a wake-up “daemon” signal from the SNMP daemon (for example, an incoming data packet).
• the internal clock may be used to trigger the CPU 100 .
• the internal clock may be utilized until the CPU 100 is fully active, at which time most or all of the clock requirements may be transitioned to external time protocols, e.g., using Internet time servers using NTP, SNTP, or other suitable time protocols from a remote time server, or using PTP and SNMP to take over the control of the clocking operations. This would mean that internal clock circuitry for CPU 100 could be turned off, thus conserving power.
• Executable instructions for the CPU 100 may be optimized to be more efficient than conventional CPUs so that much lower clock rates are used.
• a self-adjusting cycle rate may be provided depending on the load and function to be performed.
• self-learning or predetermined algorithms for expected scenarios may be utilized to put the CPU 100 into a ‘sleep’ or ‘doze’ mode.
• An expected external event may cause the CPU 100 to exit the doze mode, resume full speed operation to execute necessary operations and handle the external event, and return back to doze.
• the CPU register contents may be read and stored in special registers with long deep-sleep data maintaining capabilities. Such clock saving measures may yield substantial power savings.
• FIG. 2 illustrates an exemplary architecture 200 for a TCP/IP stack state machine-based system, according to various embodiments.
• the operating system kernel may include various components operating between applications 210 and hardware 220 .
• the kernel may include a TCP stack 232 , UDP stack 236 , and/or ICMP stack 240 , around which the operating environment may be built.
• the kernel may include TCP extensions 230 , UDP extensions 234 , ICMP extensions 238 , which together with the respective TCP stack 232 , the UDP stack 236 , and the ICMP stack 240 are shown above an IP layer 250 .
• the kernel may include one or more device drivers 260 , 262 , and 264 , as well as an Ethernet controller 270 .
• the API for all operations of the operating system may include the conventional Berkeley Sockets style API of sockets and ports on IP addresses.
• the Berkeley Sockets may specify the data structures and function calls that interact with the network subsystem of the operating system.
• the kernel may handle the normal Sockets APIs.
• the Sockets API 280 may also include some optimized APIs.
• Any non-conventional functions may be handled in a similar manner (e.g., by opening sockets and binding to ports).
• accessing of local input and output e.g., keyboards, mice, and display screens
• socket/port operations e.g., accessing of local input and output
• a keyboard could be at a local host at, for example, 127.0.0.1, or remote at another IP address.
• this transparency may be an aspect of other operating systems, it may not be inherent in the operating system design from the outset.
• the size of a basic kernel may be very small in a minimal configuration, perhaps as small as a few hundred bytes.
• the Windows Sockets technology above is mentioned merely for the purpose of providing an example. In contrast to the present technology, in the Windows Sockets technology communications with a display device over the Internet may be cumbersome.
• FIG. 3 is a flow chart illustrating an exemplary method 300 for a CPU embedding a protocol stack-based operating system.
• the method 300 may commence at operation 310 with receiving an I/O request.
• the request may be from an application residing in an applications layer 210 of a computing device.
• the network protocol may be determined.
• the protocol is TCP/IP, so that the operating system is a TCP/IP stack state machine.
• the protocol is UDP/IP.
• UDP is an unreliable connectionless protocol sitting on top of IP
• TCP is a connection-oriented reliable protocol.
• the protocol may be a hybrid of TCP and UDP, wherein a data connection stream includes a mixture of UDP and TCP packets.
• UDP has less overhead and is suitable for lower-importance information
• TCP has a higher overhead but essentially guarantees delivery.
• a stream of data comprising non-essential information (such as low-importance data) mixed with critical data could better be transmitted over such a hybrid link.
• This hybrid protocol may be determined in operation 320 .
• the I/O request may be processed according to the network protocol.
• the processing may be performed by the state machine that is the operating system (e.g., a TCP/IP stack state machine operating system).
• the operating system may utilize a Sockets style API of sockets and ports on IP addresses for handling I/O requests.
• the conventional Berkeley Sockets style API of sockets and ports on IP addresses may be used.
• the Berkeley Sockets may specify the data structures and function calls that interact with the network subsystem of the operating system.
• FIG. 4 is a block scheme of a computing device 400 , according to an exemplary embodiment.
• the computing device 400 may comprise five CPUs 410 , 412 , 414 , 416 , and 418 . Despite the fact that five CPUs are shown, it will be appreciated by one skilled in the art that any number of CPUs may be used in the computing device 400 . Some embodiments may include up to 10,000 CPUs or even more.
• the CPUs 410 , 412 , 414 , 416 , and 418 may all be coupled to a bus line 420 so that they may communicate data amongst each other.
• each CPU embeds an operating system based on a protocol stack.
• the protocol stack may be a TCP/IP protocol stack, UDP/IP stack, combinations thereof (i.e., hybrid stack), or other appropriate protocols.
• TCP/IP protocol stack UDP/IP stack
• combinations thereof i.e., hybrid stack
• the CPUs 410 , 412 , 414 , 416 , and 418 may each include a memory storing an operating system and/or any further executable instructions and/or data.
• the memory can be implemented within the CPU or externally. In one example, all CPUs 410 , 412 , 414 , 416 , and 418 may share a single memory coupled to the bus 420 .
• the term “memory” refers to any type of long term, short term, volatile, nonvolatile, or other storage devices and is not limited to any particular type of memory or number of memories, or type of media upon which memory is stored.
• the CPUs 410 , 412 , 414 , 416 , and 418 in the example in FIG. 4 may further comprise an I/O Interface (not shown) implemented as software and/or hardware.
• I/O Interface implemented as software and/or hardware.
• One particular example of software implementation of the I/O Interface is shown as optional Network Interface Module 150 in FIG. 1 .
• a hardware implementation may comprise an I/O controller, a Network Interface Controller (NIC) as an Ethernet controller, or the like. It will be apparent to those skilled in the art that the I/O interface may support any communication standards and provide communications over a serial connection, parallel connection, firewire connection, Ethernet connection, and so forth.
• Each of the CPUs may further comprise a clock (not shown), which can be implemented within each CPU or externally. According to various embodiments, a single clock may be shared by all CPUs.
• One or more of the CPUs may embed a Master Control Program (MCP) 430 .
• MCP Master Control Program
• the CPU 410 embeds the MCP 430 .
• the MCP 430 is an application or a routine for managing operations of the remaining CPUs 412 , 414 , 416 , and 418 and, therefore, the CPU 410 may be considered a “Master Core.” More specifically, the MCP 430 may be configured to receive I/O requests from outside devices, generate multiple strands (processes, tasks) according to the I/O requests, and allocate these strands (processes) to the other CPUs 412 , 414 , 416 , and 418 so that the overall computational load is selectively distributed among the CPUs 412 , 414 , 416 , and 418 .
• strands may be allocated to some of the CPUs 412 , 414 , 416 , and 418 , or to just one CPU.
• each of a number of CPUs i.e., one, some, or all of the CPUs
• the results of the computations may be assembled in the Master Core for further outputting.
• the CPUs 412 , 414 , 416 , and 418 may deliver results directly to corresponding external devices.
• the computing device 400 may comprise several Master Cores for processing different types of I/O requests.
• one Master Core may process all incoming I/O requests, while other Master Cores may be utilized for assembling the output of multiple CPUs, and transmitting of the assembled output results to corresponding outside devices.
• other Master Cores may be utilized for assembling the output of multiple CPUs, and transmitting of the assembled output results to corresponding outside devices.
• the MCP physically allocates a hardware core stack to the strand (or process).
• An allocated core stack/strand combination may also be referred to as a “core strand”.
• the cores (or core strands) may form a massive array in which core strands may be wired as a block to share resources (e.g., memory), or allowed to share the resources over their interconnects. Cores in the (massive) array of cores may be connected to each other, e.g., interconnected by a web-like structure.
• Cores may be allocated processes in some embodiments, i.e., cores which are processes or “process cores”. Such exemplary process cores are naturally isolated from other process cores since processes run independently of other processes, each process containing their own resources, in contrast to strands where resources may be shared therebetween.
• the computing device 400 allows only a certain number of CPUs to operate while the remaining CPUs, not involved in the processing, are turned off.
• the computing device 400 may comprise 1,000 CPUs and a single Master Core.
• the Master Core may generate 600 strands (variously within a number of processes) and allocate them to 600 CPUs.
• the remaining 400 CPUs may be turned off to conserve power. If another 100 strands later become needed, 100 of the 400 CPUs may be turned on in response to the allocating of the 100 strands to them so that the total number of the CPUs executing instructions becomes 700.
• the overall power consumption is reduced compared to the traditional system where all processors run all the time, even if there is no process or strand to execute.
• the computing device 400 may facilitate greater stability of operations when compared to conventional multicore processors. When one of the strands crashes, for example, due to a poorly written routine or for some other reason, only the CPU running the strand is affected, while other CPUs remain unaffected. This is in contrast to conventional systems where the entire multicore processor may become affected by a single strand crash.
• FIG. 5 illustrates an exemplary embodiment of a computing environment 500 .
• the computing environment 500 may comprise a computing device 510 (which is described in greater detail with reference to FIG. 4 ), a memory 520 , a clock 530 , and communication ports 540 , all of which may be coupled to a bus 550 .
• the memory 520 may include any memory configured to store and retrieve data. Some examples of the memory 520 include storage devices, such as a hard disk, magnetic tape, any other magnetic medium, a CD-ROM disk, digital video disk (DVD), any other optical medium, any other physical medium with patterns of marks or holes, a RAM, a ROM, a PROM, an EPROM, an EEPROM, a FLASHEPROM, OTPROM, OTP NVM, Flash ROM or any other memory chip or cartridge, or any other medium from which a computer can read instructions.
• the memory 520 may comprise a data structure configured to hold and organize data.
• the memory 520 may comprise executable instructions of the operating system and/or other routines and applications.
• the memory 520 may also comprise a MCP, as described above with reference to FIG. 4 .
• the clock 530 may serve as an asynchronous clock for the operating system for one or more CPUs of the computing device 510 .
• the asynchronous clock may be configured to automatically stop when clock cycles are not needed.
• Communication ports 540 represent a connection interface that allows asynchronous transmission of data between the computing environment 500 and any edge devices such as a keyboard, mouse, monitor, printer, CD-ROM drive, network controller, and so forth.
• the computing environment 500 may be implemented as a desktop computer, a laptop computer, a mobile telephone, a smartphone, a PDA, and many other consumer electronic devices.
• FIG. 6 is a flow chart of an exemplary method 600 for processing I/O requests by a computing device comprising multiple CPUs, with the CPUs each embedding a protocol stack-based operating systems.
• the method may commence in operation 610 , when a CPU embedding a MCP (i.e., a Master Core) receives an I/O request.
• the network protocol may be determined. According to various embodiments, the protocol is TCP/IP, UDP/IP, a combination thereof, or the like.
• the Master Core may generate multiple strands (e.g., within processes) according to the I/O requests and the determined (optional in operation 620 ) network protocol.
• the Master Core may schedule and allocate the multiple strands among one or more CPUs 412 , 414 , 416 , 418 (see FIG. 4 ) and other CPUs of the computing device. The allocation of multiple strands may include communicating data via a network interface (e.g., via a bus using I/O interfaces of the CPUs).
• the strands may be processed in the one or more CPUs.
• the processing at each CPU is performed by the state machine that is the operating system, e.g., a TCP/IP stack state machine operating system.
• the operating system may utilize Sockets style API of sockets and ports on IP addresses for handling these strands.
• processing results (e.g., arithmetical or logic results) from multiple CPUs may be assembled by the Master Core for further outputting. According to another example, assembling may be performed within a different CPU, or, alternatively, processing results may be directly transmitted to a corresponding edge device.
• protocol stack-based multiple processors which can be used in different computing devices according to various embodiments disclosed herein.
• a conventional operating system may manage internal tasks and external programs in a dictatorial manner, wherein the appearance of multitasking is achieved through rapid allocation of time slices among multiple strands and processes.
• Such a system may be flexible and of a general purpose.
• applications and unknown driver components have little or no control over their scheduling in such a system.
• the operating system In contrast to a conventional operating system, the operating system according to the various embodiments disclosed herein is essentially a state machine. This results in the whole environment being inherently cooperative and friendly to the operating system as a state machine model. All systems and application components are built together in an open and symbiotic relationship. Only components actually required in a target system are built into the environment.
• the kernel and other systems components include all the normal functions of file and memory management, timers, input and output, TCP/IP, and the like.
• the conventional operating system provides a highly sophisticated and flexible system, but with the downside of a tremendous number of activities (and hence clock cycles and, therefore, energy) going on all the time.
• an implementation according to various embodiments disclosed herein may include only the required components. As a result, execution times and code sizes may be optimized, resulting in fewer energy cycles.
• Such computing device may have a number of state machines handling the operations at a lower level and forwarding data packets up through the TCP/IP stack. When no tasks need to be performed, the state machines are idle. Therefore, the protocol stack-based CPUs according to various embodiments disclosed herein eliminate unnecessary internal clock cycles through the use of intelligent tasking, in contrast to conventional multi-tasking.
• the ultra-low power aspect of the computing device may provide greatly improved battery life for various devices.
• Boot up time for devices may be greatly reduced by executing instructions from the ROM, saving general state information in battery-backed SRAM, and saving crucial microprocessor register setting and other state information in special registers in custom application-specific integrated circuits (ASICs), for example.
• ASICs application-specific integrated circuits
• a full IP stack typically includes an application layer, transport layer, Internet layer, and link layer.
• the basic operating system for the computing device may not normally have all the components of a full IP stack.
• a basic kernel may have, for example, just HTTP on top of TCP on top of IP on top of Ethernet.
• the kernel may be built with SNMP on UDP on IP on Ethernet.
• the computing device may also attempt to identify which sub-processes in a larger process need to be executed sequentially and which sub-processes may be executable in parallel.
• the computing device may provide a model of a set of simple state machines.
• a State Machine Manager (SMM) may be provided to regulate and control the run flow.
• applications register priority and execution parameter requests with the SMM, which in turn handles them accordingly in a fair manner.
• multicore processors are designed first, and thereafter an operating system is designed to run on such processors.
• the operating system design is limited by compromises dictated by the multicore processor design.
• the applications are then designed to run on the operating system.
• the design of the applications is limited by all the limitations dictated by the particular operating system design.
• an operating system may be designed first according to the embodiments described herein. Any unnecessary aspects may be removed for the design. A computing device having multiple CPUs may then be designed. The design process may be iterated to make still further reductions down to the essential components.
• the operating system code executes within a ROM. While saving register contents during a deep sleep, execution within the ROM and as a state machine provide an “instant-on” capability where it may take just milliseconds for the system to resume execution.
• a RAM memory may be used for only truly read-write data that requires it, while the execute-only code may be stored in the ROM.
• the slower access times of ROM devices versus RAM devices may not cause an issue, because the instruction cycle times for the system are generally slow, albeit for a reduced number of cycles.
• Non-volatile media include, for example, optical or magnetic disks, such as a fixed disk.
• Volatile media include dynamic memory, such as system RAM.
• Transmission media include coaxial cables, copper wire, and fiber optics, among others, including the wires that comprise one embodiment of a bus.
• Computer-readable media include, for example, a floppy disk, a flexible disk, a hard disk, magnetic tape, any other magnetic medium, a CD-ROM disk, DVD, any other optical medium, any other physical medium with patterns of marks or holes, a RAM, a PROM, an EPROM, an EEPROM, a FLASHEPROM, any other memory chip or cartridge, or any other medium from which a computer can read.
• a bus may carry the data to system ROM (or RAM), from which a CPU retrieves and executes the instructions.
• system ROM or RAM
• the instructions received by system ROM (or RAM) may optionally be stored on a fixed disk either before or after execution by a CPU.

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• 2011
  • 2011-09-02 US US13/224,938 patent/US8904216B2/en not_active Expired - Fee Related
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• 2012
  • 2012-08-09 EP EP12827760.5A patent/EP2751700A4/en not_active Withdrawn
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