US8987734B2 - Semiconductor wafer, semiconductor process and semiconductor package - Google Patents

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• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/10—Measuring as part of the manufacturing process
  • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
  • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• • H01L27/04—
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/484—Connecting portions
  • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
  • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/181—Encapsulation

Definitions

• the present invention relates to the field of 3D semiconductor packaging, and, more particularly, to techniques and structures used to facilitate testing of conductive vias.
• stacked-chip packaging multiple integrated circuit chips can be packaged in a single package structure in a vertically stacked manner. This increases stack density, making the package structure smaller, and often reduces the length of the path that signals must traverse between chips. Thus, stacked-chip packaging tends to increase the speed of signal transmission between or among chips. Additionally, stacked-chip packaging allows chips having different functions to be integrated in a single package structure.
• TSV through silicon vias
• a semiconductor wafer is etched from its bottom surface to form a plurality of via holes such that a bottommost patterned metal layer (i.e., “metal one” (M 1 )) of the semiconductor wafer is exposed. Then, the via holes are plated with a conductive metal so as to form the through silicon vias (TSVs). The semiconductor wafer is then sawed to form semiconductor dice.
• the etchant may not etch the semiconductor wafer precisely, so that some via holes will not reach to the bottommost patterned metal layer (M 1 ).
• the plating parameter may not be controlled well, so that the thickness of the conductive metal is not even, and some conductive metal will not contact the bottommost patterned metal layer (M 1 ).
• the above two cases will result in that the conductive metal of the TSV will not stop on the bottommost patterned metal layer (M 1 ) perfectly in the plating process, and an open circuit is formed between the conductive metal and the bottommost patterned metal layer (M 1 ).
• such undesired defects are found only upon performing a test on the semiconductor die, which means such undesired defects are found only after the semiconductor wafer had been sawed into the semiconductor dice.
• the semiconductor package includes a semiconductor die, which comprises a substrate; a plurality of dielectric layers, disposed on the substrate; an integrated circuit, including a plurality of patterned metal layers disposed between the dielectric layers and electrically connected to each other; and at least one metal segment, insulated from the integrated circuit and exposed from a lateral side surface of the semiconductor die.
• the at least one metal segment is disposed on a dielectric layer which is the bottommost of the dielectric layers, at least one metal segment and a bottommost patterned metal layer of the integrated circuit each have lower surfaces which are substantially coplanar, and the semiconductor die further comprises at least one conductive via.
• the semiconductor wafer includes a substrate divided into a plurality of die areas and a plurality of trench areas; wherein each of the die areas includes an integrated circuit having a plurality of patterned metal layers disposed between dielectric layers and electrically connected to each other; and wherein the trench areas are disposed between the die areas, and at least one metal segment is disposed in the trench area and insulated from the integrated circuit of an adjacent die area.
• the at least one metal segment is disposed on a bottommost dielectric layer, and the at least one metal segment and a bottommost patterned metal layer are coplanar at the same layer.
• the semiconductor process comprises (a) providing a semiconductor wafer having a substrate, at least one metal segment, a plurality of integrated circuits and a plurality of dielectric layers, wherein the at least one metal segment, the integrated circuits and the dielectric layers are disposed on a top surface of the substrate, each of the integrated circuits includes a plurality of patterned metal layers disposed between the dielectric layers and electrically connected to each other, and the at least one metal segment is insulated from the integrated circuits; (b) forming a plurality of testing holes and inner holes from a bottom surface of the substrate to expose the at least one metal segment and a bottommost patterned metal layer of the integrated circuit, respectively; (c) forming a plurality of conductive metals in the testing holes and the inner holes, wherein the conductive metals in the testing holes are separated from each other; and (d) probing at least two of the conductive metals in two of the testing holes.
• the semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has each of the integrated circuits, and the trench areas are disposed between the die areas.
• the at least one metal segment is disposed in the trench area.
• the at least one metal segment is disposed in the die areas.
• the at least one metal segment can be disposed on a bottommost dielectric layer, the at least one metal segment and a bottommost patterned metal layer of the integrated circuit are coplanar at the same layer.
• the conductive metals can be plated on a sidewall of each of the testing holes and a sidewall of each of the inner holes.
• the conductive metals can fill the testing holes and the inner holes, the conductive metals in the testing holes can further extend to the bottom surface of the substrate to form a plurality of testing portions used to be probed in step (d), and the conductive metals in the testing holes can contact the at least one metal segment, and the conductive metals in the inner holes contact the bottommost patterned metal layer of the integrated circuit.
• the semiconductor process further includes the step of sawing the semiconductor wafer along the trench areas to form a plurality of semiconductor die. During the sawing process, the at least one metal segment and the conductive metals in the testing holes may be removed.
• FIG. 1 illustrates a cross-sectional view of a semiconductor package according to an embodiment of the present invention
• FIGS. 2 to 16 illustrate a process for making a semiconductor die according to an embodiment of the present invention
• FIG. 17 illustrates a process for making a semiconductor die according to another embodiment of the present invention.
• FIGS. 18 and 19 illustrate a bottom view and a side view, respectively, of a semiconductor die according to another embodiment of the present invention.
• FIG. 20 illustrates a partially enlarged bottom view of a semiconductor wafer having a metal segment according to another embodiment of the present invention
• FIG. 21 illustrates a partially enlarged bottom view of a semiconductor wafer having the metal segment according to another embodiment of the present invention.
• FIG. 22 illustrates a partially enlarged bottom view of a semiconductor wafer having the metal segment according to another embodiment of the present invention.
• FIG. 23 illustrates a partially enlarged bottom view of semiconductor wafer probing of the metal segment according to another embodiment of the present invention.
• the semiconductor package 1 comprises a package substrate 11 , a semiconductor die 3 , a plurality of bonding wires 12 , a molding compound 14 and a solder layer 16 .
• the package substrate 11 has a top surface 111 and a bottom surface 112 .
• the semiconductor die 3 is disposed on the top surface 111 of the package substrate 11 .
• the semiconductor die 3 comprises a substrate 40 , a plurality of dielectric layers 481 , 482 , 483 , 484 , an integrated circuit 20 , a part of a metal segment 46 , four side surfaces 31 and a plurality of conductive vias 28 .
• the substrate 40 has a top surface 401 and a bottom surface 402 .
• the metal segment 46 and the dielectric layers 481 , 482 , 483 , 484 are disposed on the top surface 401 of the substrate 40 .
• the bottommost dielectric layer 481 is directly disposed on the top surface 401 of the substrate 40 , and the second dielectric layer 482 , the third dielectric layer 483 and the fourth dielectric layer 484 are disposed on the bottommost dielectric layer 481 , in this order.
• the integrated circuit 20 includes a plurality of patterned metal layers 201 , 202 , 203 and a plurality of interconnection metals 204 .
• the patterned metal layers 201 , 202 , 203 are disposed between the dielectric layers 481 , 482 , 483 , 484 and electrically connected to each other.
• the metal segment 46 is insulated from the integrated circuit 20 . That is, the metal segment 46 is not electrically connected to the integrated circuit 20 .
• the metal segment 46 and the bottommost patterned metal layer 201 of the integrated circuit 20 are substantially coplanar at the same layer. It is noted that the integrated circuit 20 is not exposed from the four side surfaces 31 of the semiconductor die 3 , but part of the metal segment 46 is exposed from a side surface 31 of the semiconductor die 3 .
• the solder layer 16 is used for bonding the bottom surface 402 of the substrate 40 of the semiconductor die 3 to the top surface 111 of the package substrate 11 .
• a portion of the solder layer 16 may fill part of the central hole defined by the conductive metal 26 in the conductive via 28 .
• the integrated circuit 20 is electrically connected to the package substrate 11 through the conductive via 28 and the solder layer 16 for grounding such that the inductance is low.
• the bonding wires 12 electrically connect the third patterned metal layer 203 of the integrated circuit 20 and the top surfaces 111 of the package substrate 11 .
• the molding compound 14 encapsulates the semiconductor die 3 , the bonding wires 12 and a part of the package substrate 11 .
• a process for making a semiconductor die according to an embodiment of the present invention is illustrated.
• a semiconductor wafer 4 is provided, wherein a bottom view of the semiconductor wafer 4 , according to an embodiment of the present invention, is illustrated.
• the semiconductor wafer 4 is defined as a plurality of die areas 42 and a plurality of trench areas 44 .
• the die areas 42 are predetermined, arranged in an array, and will become each of the semiconductor die 3 ( FIG. 1 ) after the semiconductor wafer 4 is sawed.
• the trench areas 44 are disposed between the die areas 42 .
• the trench areas 44 include “saw streets” that will be removed during the sawing step.
• the semiconductor wafer 4 comprises at least one metal segment 46 .
• the metal segment 46 is disposed in the trench area 44 .
• the metal segment 46 may be disposed in the die area 42 .
• the semiconductor wafer 4 comprises a substrate 40 , the metal segment 46 and a plurality of dielectric layers.
• the material of the substrate 40 is a semiconductor material such as silicon or germanium.
• the substrate 40 has a top surface 401 and a bottom surface 402 .
• the metal segment 46 and the dielectric layers are disposed on the top surface 401 of the substrate 40 .
• the dielectric layers are inter-level dielectrics which include, but are not limited to, a bottommost dielectric layer 481 , a second dielectric layer 482 , a third dielectric layer 483 and a fourth dielectric layer 484 .
• Each of the dielectric layers 481 , 482 , 483 , 484 may comprise a dielectric layer with a low dielectric constant (K) (less than 3.4) or an ultra-low dielectric constant (K) (less than 2.5), and the material of the dielectric layers 481 , 482 , 483 , 484 may be the same as, or different from, each other.
• the bottommost dielectric layer 481 is directly disposed on the top surface 401 of the substrate 40 , and the second dielectric layer 482 , the third dielectric layer 483 and the fourth dielectric layer 484 are disposed on the bottommost dielectric layer 481 in sequence.
• the second dielectric layer 482 has a plurality of openings 4821
• the third dielectric layer 483 has a plurality of openings 4831
• the fourth dielectric layer 484 has a plurality of openings 4841 .
• the die area 42 has an integrated circuit 20 including a plurality of patterned metal layers and a plurality of interconnection metals 204 .
• the patterned metal layers include, but are not limited to, a bottommost patterned metal layer 201 , a second patterned metal layer 202 and a third patterned metal layer 203 .
• the patterned metal layers 201 , 202 , 203 are disposed between the dielectric layers 481 , 482 , 483 , 484 and electrically connected to each other.
• the material of the patterned metal layers 201 , 202 , 203 is copper (Cu).
• the bottommost patterned metal layer 201 is disposed on the bottommost dielectric layer 481 , and covered by the second dielectric layer 482 .
• the second patterned metal layer 202 is disposed on the second dielectric layer 482 , and covered by the third dielectric layer 483 .
• the interconnection metals 204 are disposed in the openings 4821 of the second dielectric layer 482 for electrically connecting the bottommost patterned metal layer 201 and the second patterned metal layer 202 .
• the third patterned metal layer 203 is disposed in the openings 4831 of the third dielectric layer 483 for electrically connecting the second patterned metal layer 202 .
• the openings 4841 of the fourth dielectric layer 484 expose the third patterned metal layer 203 .
• the metal segment 46 is disposed in the trench area 44 and is insulated from the integrated circuit 20 of the die area 42 . That is, the metal segment 46 is not electrically connected to the integrated circuit 20 .
• the metal segment 46 is disposed on the bottommost dielectric layer 481 directly. That is, the metal segment 46 and the bottommost patterned metal layer 201 of the integrated circuit 20 are coplanar at the same layer, and they are formed at the same time with the same material.
• the metal segment 46 is disposed in the die area 42 but is insulated from the integrated circuit 20 . It is noted that the metal segment 46 is not a part of the bottommost patterned metal layer 201 .
• FIG. 4 a cross-sectional view taken along line 4 - 4 of FIG. 2 is illustrated.
• the metal segment 46 is disposed within the trench area 44 , and there is no patterned metal layer disposed above the metal segment 46 .
• the second patterned metal layer 202 may be disposed above the metal segment 46 .
• the metal segment 46 includes three pad portions 461 and two connecting portions 462 .
• the connecting portions 462 connect the pad portions 461 .
• the width of the connecting portion 462 is less than that of the pad portion 461 .
• the metal segment 46 is rectangular and has an equal width.
• a plurality of testing holes 22 are formed from the bottom surface 402 of the substrate 40 by etching to expose the metal segment 46 .
• the testing holes 22 extend through the substrate 40 and the bottommost dielectric layer 481 .
• one metal segment 46 corresponds to three testing holes 22 .
• FIG. 8 a bottom view of FIG. 7 is illustrated.
• Each of the pad portions 461 corresponds to each of the testing holes 22 .
• a plurality of inner holes 24 are formed from the bottom surface 402 of the substrate 40 by etching to expose the bottommost patterned metal layer 201 of the integrated circuit 20 in the die area 42 .
• the inner holes 24 extend through the substrate 40 and the bottommost dielectric layer 481 .
• the diameter of the inner hole 24 is about equal to that of the testing hole 22 .
• the diameter of the inner hole 24 is different from that of the testing hole 22 .
• a plurality of conductive metals 26 are formed in the testing holes 22 by plating so as to form a plurality of testing vias 27 in the testing holes 22 .
• the material of the conductive metals 26 is copper (Cu).
• the conductive metals 26 contact the metal segment 46 so that the conductive metals 26 situate on the metal segment 46 .
• the conductive metals 26 in the testing holes 22 are separated from each other. That is, they are not physically connected to each other.
• the conductive metals 26 in the testing holes 22 further extend to the bottom surface 402 of the substrate 40 to form a plurality of testing portions 261 for which can be probed.
• the conductive metals 26 are plated on a sidewall of each of the testing holes 22 .
• the conductive metals 26 fill the testing holes 22 .
• Each of the conductive metals 26 has one testing portion 261 .
• the conductive metals 26 contact the metal segment 46 .
• the conductive metals 26 are also formed in the inner holes 24 by plating so as to form a plurality of conductive vias 28 in the inner holes 24 .
• the conductive metals 26 contact the bottommost patterned metal layer 201 so that the conductive metals 26 end on the bottommost patterned metal layer 201 .
• the conductive metals 26 are plated on a sidewall of each of the inner holes 24 .
• the conductive metals 26 fill the inner holes 24 .
• any two of the conductive metals 26 in two of the testing holes 22 are probed by using two probes 29 .
• two probes 29 are used to contact two testing portions 261 respectively. If the conductive metals 26 in the two testing holes 22 create a short circuit (e.g., as determined by the measured resistance between the two probes 29 being lower than 100 ⁇ ), it is confirmed that the conductive metals 26 in the testing holes 22 situate on the metal segment 46 perfectly, and the conductive metals 26 in the inner holes 24 are presumed to stop on the bottommost patterned metal layer 201 perfectly. Furthermore, the conductive metal 28 and the conductive vias 26 are near to each other and formed simultaneously.
• the conductive metals 28 can be presumed to stop on metal as well. Accordingly, the conductive vias 28 are determined to be formed properly and therefore “qualified”; the semiconductor wafer 4 can then be sawed or delivered. If the conductive metals 26 in the two testing holes 22 create an open circuit (e.g., as determined by the measured resistance between the two probes 29 being greater than or equal to 100 ⁇ ), it is confirmed that the conductive metals 26 in the testing holes 22 do not contact the metal segment 46 , and additionally, it is presumed that the conductive metals 26 in the inner holes 24 fail to stop on the bottommost patterned metal layer 201 . Furthermore, the conductive metal 28 and the conductive vias 26 are near to each other and formed simultaneously.
• the conductive metals 26 When the conductive metals 26 are presumed to fail to stop on metal, the conductive metals 28 can be presumed failing to stop on metal as well. Therefore, the conductive vias 28 can be determined to be “unqualified.” Therefore, the undesired defect of the unqualified conductive vias 28 is found before the semiconductor wafer 4 has been sawed or delivered. Thus, the wafer can be selected in time if such undesired defect happens and the yield of the wafer can be significantly enhanced.
• the semiconductor wafer 4 is sawed along the trench areas 44 to remove a part of the metal segment 46 and the testing vias 27 to form a plurality of semiconductor dice 3 ( FIGS. 15 and 16 ).
• the trench areas 44 are predetermined sawing streets, however, in the actual sawing process, the semiconductor wafer 4 is sawed along the real cutting paths 30 .
• the real cutting path 30 is disposed within the trench area 44 , and the width of the real cutting path 30 is narrower than that of the trench area 44 . In this embodiment, the width of the real cutting path 30 is narrower than that of the metal segment 46 , but is greater than that of the testing via 27 so that the testing via 27 is cut away but another part of the metal segment 46 remains.
• the semiconductor die 3 comprises the substrate 40 , the dielectric layers 481 , 482 , 483 , 484 , the integrated circuit 20 , a part of the metal segment 46 , four side surfaces 31 and the conductive vias 28 .
• the substrate 40 has a top surface 401 and a bottom surface 402 .
• the metal segment 46 and the dielectric layers 481 , 482 , 483 , 484 are disposed on the top surface 401 of the substrate 40 .
• the bottommost dielectric layer 481 is directly disposed on the top surface 401 of the substrate 40 , and the second dielectric layer 482 , the third dielectric layer 483 and the fourth dielectric layer 484 are disposed on the bottommost dielectric layer 481 in sequence.
• the integrated circuit 20 ( FIG. 3 ) is disposed with the die area 42 , and includes the patterned metal layers 201 , 202 , 203 and the interconnection metals 204 .
• the patterned metal layers 201 , 202 , 203 are disposed between the dielectric layers 481 , 482 , 483 , 484 and electrically connected to each other.
• the metal segment 46 is insulated from the integrated circuit 20 of the die area 12 .
• the metal segment 46 is not electrically connected to the integrated circuit 20 .
• the metal segment 46 is disposed on the bottommost dielectric layer 201 directly. That is, the metal segment 46 and the bottommost patterned metal layer 201 of the integrated circuit 20 are at the same layer.
• the real die area of the semiconductor die 3 is defined by the four side surfaces 31 , and is larger than the die area 42 . It is noted that the integrated circuit 20 is not exposed from the four side surfaces 31 of the semiconductor die 3 , but the part of the metal segment 46 is exposed from a lateral side surface 31 of the semiconductor die 3 .
• FIG. 17 a process for making a semiconductor die according to another embodiment of the present invention is illustrated.
• the semiconductor process of this embodiment is similar to the semiconductor process of FIGS. 2 to 16 , and the difference involves the sawing process.
• the semiconductor wafer 4 is sawed along the trench areas 44 to remove the metal segment 46 and the testing vias 27 to form a plurality of semiconductor dice 3 a ( FIGS. 18 and 19 ).
• the trench areas 44 are predetermined sawing streets, however, in actual sawing process, the semiconductor wafer 4 is sawed along the real cutting paths 30 a .
• the real cutting path 30 a is narrower than that of the real cutting paths 30 of FIG. 14 , and the width of the real cutting path 30 a is less than the diameter of the testing via 27 . Therefore, a part of the testing via 27 is not cut away so that a part of the testing via 27 and a part of the metal segment 46 remain.
• FIGS. 18 and 19 a bottom view and a side view of a semiconductor die according to another embodiment of the present invention are illustrated.
• the semiconductor die 3 a of this embodiment is substantially similar to the semiconductor die 3 of FIGS. 15 and 16 , and the difference between the semiconductor die 3 a of this embodiment and the semiconductor die 3 of FIGS. 15 and 16 is described as follows.
• the semiconductor die 3 a further comprises the conductive metal 26 extending from the metal segment 46 to the bottom surface 402 of the substrate 40 .
• the metal segment 46 and the testing via 27 are exposed from the side surface 31 of the semiconductor die 3 a .
• the semiconductor die 3 of FIG. 1 may be replaced by the semiconductor die 3 a of FIGS. 18 and 19 .
• FIG. 20 a partially enlarged bottom view of a semiconductor wafer having the metal segment according to another embodiment of the present invention is illustrated.
• the semiconductor wafer 4 a of this embodiment is substantially similar to the semiconductor wafer 4 of FIG. 2 , and the difference between the semiconductor wafer 4 a of this embodiment and the semiconductor wafer 1 of FIG. 2 is described as follows.
• the metal segment 46 a of this embodiment is in a cross shape, and is disposed between four die areas 42 .
• the positions of the testing vias 27 correspond to the four branches of the metal segment 46 a respectively.
• FIG. 21 a partially enlarged bottom view of a semiconductor wafer having the metal segment according to another embodiment of the present invention is illustrated.
• the semiconductor wafer 4 b of this embodiment is substantially similar to the semiconductor wafer 4 of FIG. 2 , and the difference between the semiconductor wafer 4 b of this embodiment and the semiconductor wafer 1 of FIG. 2 is described as follows.
• the metal segment 46 b of this embodiment is in an L-shape, and is disposed around a corner of the die area 42 .
• the positions of the testing vias 27 correspond to the end portions of the metal segment 46 b respectively.
• FIG. 22 a partially enlarged bottom view of a semiconductor wafer having the metal segment according to another embodiment of the present invention is illustrated.
• the semiconductor wafer 4 c of this embodiment is substantially similar to the semiconductor wafer 4 b of FIG. 21 , and the difference between the semiconductor wafer 4 c of this embodiment and the semiconductor wafer 4 b of FIG. 21 is described as follows.
• At least one of the die areas 42 has a notch 421 , and is not rectangular. That is, the die areas 42 are not arranged in an array.
• the metal segment 46 c of this embodiment further has a protrusion portion 463 corresponding to the notch 421 .
• At least one of the testing vias 27 is disposed at the position corresponding to the protrusion portion 463 . It is noted that the protrusion portion 463 is not disposed in the sawing streets, thus, the protrusion portion 463 and the testing via 27 corresponding to the protrusion portion 463 may not be cut off during the sawing process.
• the first probing path 51 is from the testing via 271 to the testing via 272 , wherein the metal segment of the first probing path 51 is in a L shape, and is disposed around a corner of the die area 42 .
• the second probing path 52 is from the testing via 273 to the testing via 274 , wherein the metal segment of the second probing path 52 is in a C shape, and is disposed around two corners of the die area 42 .
• the third probing path 53 is from the testing via 275 to the testing via 276 , wherein the metal segment of the third probing path 53 is in a L shape, and is disposed around a corner of the die area 42 .
• the fourth probing path 54 is from the testing via 277 to the testing via 278 , wherein the metal segment of the fourth probing path 54 is in a U shape, and is disposed around two corners of the die area 42 .

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Automation & Control Theory (AREA)
• Semiconductor Integrated Circuits (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)

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• 2013
  • 2013-03-15 US US13/843,304 patent/US8987734B2/en active Active
• 2014
  • 2014-03-07 TW TW103108020A patent/TWI533415B/en active
  • 2014-03-12 CN CN201410091315.1A patent/CN104051392B/en active Active

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