US9367073B2 - Voltage regulator - Google Patents

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• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current 
  • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
  • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current 
  • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
  • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
  • G05F1/565—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
  • G05F1/567—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

Definitions

• the present invention relates to a voltage regulator including a leakage current control circuit configured to prevent an increase in output voltage caused by a leakage current of an output transistor.
• FIG. 7 is a circuit diagram illustrating a related-art voltage regulator.
• the related-art voltage regulator includes PMOS transistors 103 , 104 , 106 , 108 , 111 , and 121 , NMOS transistors 105 , 107 , 109 , 114 , and 122 , resistors 112 and 113 , capacitors 801 and 802 , a reference voltage circuit 131 , a constant current circuit 110 , a ground terminal 100 , a power supply terminal 101 , and an output terminal 102 .
• the PMOS transistors 103 , 104 , 106 , and 108 , the NMOS transistors 105 , 107 , 109 , and 114 , and the constant current circuit 110 form an error amplifier circuit.
• the capacitor 801 directly feeds back an output voltage Vout of the output terminal 102 to the inside of the error amplifier circuit.
• a zero point fzcp is added in a high frequency region in frequency characteristics of the voltage regulator.
• a zero point fzfb can be set on the low frequency side, and hence a sufficient phase margin can be obtained even in a voltage regulator of three-stage amplification.
• the setting of the zero point fzfb on the low frequency side can improve power supply rejection ratio (PSRR) characteristics as well.
• PSRR power supply rejection ratio
• a low equivalent series resistance (ESR) ceramic capacitor can be used for an output capacitor, to thereby obtain an output voltage Vout with a small ripple (see, for example, FIG. 10 of Japanese Patent Application Laid-open No. 2006-127225).
• the related-art voltage regulator however, has a problem in that, at high temperature and under a light load state in which a small load is connected to the output terminal 102 , the output voltage Vout is increased due to a leakage current Ileak from the PMOS transistor 111 .
• the present invention has been made in view of the above-mentioned problem, and provides a voltage regulator capable of preventing an output voltage from being increased due to a leakage current under a light load state.
• a voltage regulator according to one embodiment of the present invention has the following configuration.
• the voltage regulator includes a leakage current control circuit.
• the leakage current control circuit includes an NMOS transistor connected to an output terminal of the voltage regulator. When an output voltage of the voltage regulator increases due to a leakage current of an output transistor, the leakage current control circuit causes the leakage current to flow through the NMOS transistor, to thereby prevent an increase in output voltage.
• the transistor is connected to the output terminal, and when the output voltage of the voltage regulator increases due to the leakage current under a light load state, the leakage current is caused to flow through the transistor. Consequently, the output voltage can be prevented from being increased.
• FIG. 1 is a circuit diagram illustrating a configuration of a voltage regulator according to a first embodiment of the present invention.
• FIG. 2 is a circuit diagram illustrating another example of the voltage regulator according to the first embodiment.
• FIG. 3 is a circuit diagram illustrating another example of the voltage regulator according to the first embodiment.
• FIG. 4 is a circuit diagram illustrating a configuration of a voltage regulator according to a second embodiment of the present invention.
• FIG. 5 is a circuit diagram illustrating another example of the voltage regulator according to the second embodiment.
• FIG. 6 is a circuit diagram illustrating another example of the voltage regulator according to the second embodiment.
• FIG. 7 is a circuit diagram illustrating a configuration of a related-art voltage regulator.
• FIG. 1 is a circuit diagram of a voltage regulator according to a first embodiment of the present invention.
• the voltage regulator of the first embodiment includes PMOS transistors 103 , 104 , 106 , 108 , 121 , and 111 , NMOS transistors 105 , 107 , 109 , 114 , 122 , and 123 , resistors 112 and 113 , a reference voltage circuit 131 , a constant current circuit 110 , a ground terminal 100 , a power supply terminal 101 , and an output terminal 102 .
• the PMOS transistors 103 , 104 , 106 , and 108 , the NMOS transistors 105 , 107 , 109 , and 114 , and the constant current circuit 110 form an error amplifier circuit.
• the PMOS transistor 121 and the NMOS transistors 123 and 122 form a leakage current control circuit.
• the reference voltage circuit 131 has a positive terminal connected to a gate of the NMOS transistor 105 and a negative terminal connected to the ground terminal 100 .
• the NMOS transistor 105 has a source connected to a source of the NMOS transistor 107 and a drain connected to a gate and a drain of the PMOS transistor 104 .
• the PMOS transistor 104 has a source connected to the power supply terminal 101 .
• the constant current circuit 110 has one terminal connected to the source of the NMOS transistor 105 and the other terminal connected to the ground terminal 100 .
• the PMOS transistor 103 has a gate connected to the gate and the drain of the PMOS transistor 104 , a drain connected to a gate and a drain of the NMOS transistor 114 , and a source connected to the power supply terminal 101 .
• the NMOS transistor 114 has a source connected to the ground terminal 100 .
• the NMOS transistor 109 has a gate connected to the gate and the drain of the NMOS transistor 114 , a drain connected to a drain of the PMOS transistor 108 , and a source connected to the ground terminal 100 .
• the PMOS transistor 108 has a gate connected to a gate and a drain of the PMOS transistor 106 and a source connected to the power supply terminal 101 .
• the PMOS transistor 106 has a source connected to the power supply terminal 101 .
• the NMOS transistor 107 has a gate connected to a connection point of one terminal of the resistor 113 and one terminal of the resistor 112 , and a drain connected to the gate and the drain of the PMOS transistor 106 .
• the other terminal of the resistor 113 is connected to the output terminal 102 , and the other terminal of the resistor 112 is connected to the ground terminal 100 .
• the PMOS transistor 121 has a gate connected to the gate of the PMOS transistor 108 , a drain connected to a drain of the NMOS transistor 122 , and a source connected to the power supply terminal 101 .
• the NMOS transistor 122 has a gate connected to the gate of the NMOS transistor 109 and a source connected to the ground terminal 100 .
• the NMOS transistor 123 has a gate connected to the drain of the NMOS transistor 122 , a drain connected to the output terminal 102 , and a source connected to the ground terminal 100 .
• the PMOS transistor 111 has a gate connected to the drain of the PMOS transistor 108 , a drain connected to the output terminal 102 , and a source connected to the power supply terminal 101 .
• the voltage regulator When the power supply terminal 101 inputs a power supply voltage VDD, the voltage regulator outputs an output voltage Vout from the output terminal 102 .
• the resistors 112 and 113 divide the output voltage Vout and output a feedback voltage Vfb.
• the error amplifier circuit compares a reference voltage Vref of the reference voltage circuit 131 and the feedback voltage Vfb, and controls a gate voltage of the PMOS transistor 111 , which operates as an output transistor, so that the output voltage Vout becomes constant.
• the voltage regulator operates to control the output voltage Vout to be constant.
• a current flowing through the PMOS transistor 121 is represented by 12
• a current flowing through the NMOS transistor 122 is represented by Il
• a current flowing through the NMOS transistor 123 is represented by I 3 .
• Vref ⁇ Vfb is established
• a current flowing through the NMOS transistor 105 and a current flowing through the NMOS transistor 107 are equal to each other.
• the currents I 2 and I 1 obtained by returning the current of the NMOS transistor 105 and the NMOS transistor 107 are set so as to satisfy I 1 >I 2 , and then the gate of the NMOS transistor 123 becomes the ground level. Accordingly, the NMOS transistor 123 is turned off, and no current flows.
• a resistance value of the resistor 113 is represented by RF
• a resistance value of the resistor 112 is represented by RS
• a resistance value of a load (not shown) connected to the output terminal 102 is represented by RL.
• the error amplifier circuit When the feedback voltage Vfb becomes higher than the reference voltage Vref, the error amplifier circuit increases the gate voltage of the PMOS transistor 111 to reduce an output current. When the feedback voltage Vfb becomes still higher than the reference voltage Vref, the error amplifier circuit turns off the PMOS transistor 111 . However, when the leakage current Ileak is large under the high temperature state, the voltage of Ileak ⁇ RL ⁇ (RF+RS)/(RL+RF+RS) becomes higher than a desired output voltage Vout. In this state, the error amplifier circuit cannot control the output voltage Vout, and the output voltage Vout becomes higher than a desired voltage.
• the leakage current Ileak of the PMOS transistor 111 increases so that the feedback voltage Vfb becomes higher than the reference voltage Vref, the current flowing through the NMOS transistor 105 decreases, and the current flowing through the NMOS transistor 107 increases. Accordingly, when the current I 1 decreases and the current I 2 increases, the gate voltage of the NMOS transistor 123 increases, and the NMOS transistor 123 causes the current I 3 to flow therethrough.
• the leakage current Ileak of the PMOS transistor 111 is extracted as the current I 3 from the output terminal 102 . Consequently, the leakage current Ileak does not flow through the resistors 112 and 113 and the load, and the increase in output voltage Vout can be suppressed.
• the output voltage Vout increases, because a negative feedback circuit for increasing the gate voltage of the NMOS transistor 123 to be higher than the output voltage Vout is formed, the output voltage Vout slightly higher than a target value is output due to the operation of the leakage current control circuit under the light load state at high temperature.
• the description of this embodiment is directed to the high temperature state, but the leakage current control circuit can be caused to operate as long as the leakage current Ileak is generated at the output transistor, and hence the increase in output voltage Vout can be suppressed even in other cases than the high temperature state.
• the NMOS transistor 123 is connected to the output terminal 102 so that the leakage current Ileak may flow through the NMOS transistor 123 when the output voltage Vout is increased due to the leakage current Ileak of the PMOS transistor 111 . Consequently, the output voltage Vout can be prevented from being increased.
• FIG. 2 is a circuit diagram illustrating another example of the voltage regulator according to the first embodiment.
• FIG. 2 differs from FIG. 1 in that a constant current circuit 301 is added to the source of the NMOS transistor 123 .
• the gain of the negative feedback circuit is reduced, and hence the negative feedback circuit can be prevented from oscillating. Consequently, a more stable voltage regulator can be constructed.
• FIG. 3 is a circuit diagram illustrating another example of the voltage regulator according to the first embodiment. Even when a resistor 401 is added to the source of the NMOS transistor 123 in this manner, the same effect can be obtained.
• FIG. 4 is a circuit diagram of a voltage regulator according to a second embodiment of the present invention.
• the second embodiment differs from the first embodiment in that PMOS transistors are used for the input stage of the error amplifier circuit.
• the voltage regulator of the second embodiment includes PMOS transistors 501 , 502 , 505 , 508 , 121 , and 111 , NMOS transistors 503 , 504 , 506 , 507 , 122 , and 123 , resistors 112 and 113 , a reference voltage circuit 511 , a constant current circuit 512 , a ground terminal 100 , a power supply terminal 101 , and an output terminal 102 .
• the PMOS transistors 501 , 502 , 505 , and 508 , and the NMOS transistors 503 , 504 , 506 , and 507 , and the constant current circuit 512 form an error amplifier circuit.
• the PMOS transistor 121 and the NMOS transistors 123 and 122 form a leakage current control circuit.
• the reference voltage circuit 511 has a positive terminal connected to a gate of the PMOS transistor 502 and a negative terminal connected to the ground terminal 100 .
• the PMOS transistor 502 has a source connected to a source of the PMOS transistor 505 and a drain connected to a gate and a drain of the NMOS transistor 504 .
• the NMOS transistor 504 has a source connected to the ground terminal 100 .
• the constant current circuit 512 has one terminal connected to the source of the PMOS transistor 505 and the other terminal connected to the power supply terminal 101 .
• the NMOS transistor 503 has a gate connected to the gate and the drain of the NMOS transistor 504 , a drain connected to a gate and a drain of the PMOS transistor 501 , and a source connected to the ground terminal 100 .
• the PMOS transistor 501 has a source connected to the power supply terminal 101 .
• the PMOS transistor 508 has a gate connected to the gate and the drain of the PMOS transistor 501 , a drain connected to a drain of the NMOS transistor 507 , and a source connected to the power supply terminal 101 .
• the NMOS transistor 507 has a gate connected to a gate and a drain of the NMOS transistor 506 and a source connected to the ground terminal 100 .
• the NMOS transistor 506 has a source connected to the ground terminal 100 .
• the PMOS transistor 505 has a gate connected to a connection point of one terminal of the resistor 113 and one terminal of the resistor 112 , and a drain connected to the gate and the drain of the NMOS transistor 506 .
• the other terminal of the resistor 113 is connected to the output terminal 102
• the other terminal of the resistor 112 is connected to the ground terminal 100 .
• the PMOS transistor 121 has a gate connected to the gate and the drain of the PMOS transistor 501 , a drain connected to a drain of the NMOS transistor 122 , and a source connected to the power supply terminal 101 .
• the NMOS transistor 122 has a gate connected to the gate of the NMOS transistor 507 and a source connected to the ground terminal 100 .
• the NMOS transistor 123 has a gate connected to the drain of the NMOS transistor 122 , a drain connected to the output terminal 102 , and a source connected to the ground terminal 100 .
• the PMOS transistor 111 has a gate connected to the drain of the PMOS transistor 508 , a drain connected to the output terminal 102 , and a source connected to the power supply terminal 101 .
• the voltage regulator When the power supply terminal 101 inputs a power supply voltage VDD, the voltage regulator outputs an output voltage Vout from the output terminal 102 .
• the resistors 112 and 113 divide the output voltage Vout and output a feedback voltage Vfb.
• the error amplifier circuit compares a reference voltage Vref of the reference voltage circuit 511 and the feedback voltage Vfb, and controls a gate voltage of the PMOS transistor 111 , which operates as an output transistor, so that the output voltage Vout becomes constant.
• the voltage regulator operates to control the output voltage Vout to be constant.
• a current flowing through the PMOS transistor 121 is represented by I 2
• a current flowing through the NMOS transistor 122 is represented by I 1
• a current flowing through the NMOS transistor 123 is represented by I 3 .
• Vref ⁇ Vfb is established, and a current flowing through the PMOS transistor 502 and a current flowing through the PMOS transistor 505 are equal to each other.
• the currents I 2 and I 1 obtained by returning the current of the PMOS transistor 502 and the PMOS transistor 505 are set so as to satisfy I 1 >I 2 , and then the gate of the NMOS transistor 123 becomes the ground level. Accordingly, the NMOS transistor 123 is turned off, and no current flows.
• a resistance value of the resistor 113 is represented by RF
• a resistance value of the resistor 112 is represented by RS
• a resistance value of a small load (not shown) connected to the output terminal 102 is represented by RL.
• the error amplifier circuit When the feedback voltage Vfb becomes higher than the reference voltage Vref, the error amplifier circuit increases the gate voltage of the PMOS transistor 111 to reduce an output current. When the feedback voltage Vfb becomes still higher than the reference voltage Vref, the error amplifier circuit turns off the PMOS transistor 111 . However, when the leakage current Ileak is large under the high temperature state, the voltage of Ileak ⁇ RL ⁇ (RF+RS)/(RL+RF+RS) becomes higher than a desired output voltage Vout. In this state, the error amplifier circuit cannot control the output voltage Vout, and the output voltage Vout becomes higher than a desired voltage.
• the leakage current Ileak of the PMOS transistor 111 increases so that the feedback voltage Vfb becomes higher than the reference voltage Vref, the current flowing through the NMOS transistor 105 decreases, and the current flowing through the NMOS transistor 107 increases. Accordingly, when the current I 1 decreases and the current I 2 increases, the gate voltage of the NMOS transistor 123 increases, and the NMOS transistor 123 causes the current I 3 to flow therethrough.
• the leakage current Ileak of the PMOS transistor 111 is extracted as the current I 3 from the output terminal 102 . Consequently, the leakage current Ileak does not flow through the resistors 112 and 113 and the load, and the increase in output voltage Vout can be suppressed.
• the output voltage Vout increases, because a negative feedback circuit for increasing the gate voltage of the NMOS transistor 123 to be higher than the output voltage Vout is formed, the output voltage Vout slightly higher than a target value is output due to the operation of the leakage current control circuit under the light load state at high temperature.
• the description of this embodiment is directed to the high temperature state, but the leakage current control circuit can be caused to operate as long as the leakage current Ileak is generated at the output transistor, and hence the increase in output voltage Vout can be suppressed even in other cases than the high temperature state.
• the NMOS transistor 123 is connected to the output terminal 102 so that the leakage current Ileak may flow through the NMOS transistor 123 when the output voltage Vout is increased due to the leakage current Ileak of the PMOS transistor 111 . Consequently, the output voltage Vout can be prevented from being increased.
• FIG. 5 is a circuit diagram illustrating another example of the voltage regulator according to the second embodiment.
• FIG. 5 differs from FIG. 4 in that a constant current circuit 601 is added to the source of the NMOS transistor 123 .
• the gain of the negative feedback circuit is reduced, and hence the negative feedback circuit can be prevented from oscillating. Consequently, a more stable voltage regulator can be constructed.
• FIG. 6 is a circuit diagram illustrating another example of the voltage regulator according to the second embodiment. Even when a resistor 701 is added to the source of the NMOS transistor 123 in this manner, the same effect can be obtained.

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• 2013
  • 2013-12-18 JP JP2013261384A patent/JP6266333B2/en active Active
• 2014
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  • 2014-12-11 KR KR1020140178269A patent/KR102225714B1/en active Active
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