US9598772B2 - Method for fabricating bump structure without UBM undercut - Google Patents

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• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
  • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
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  • C23C18/1605—Process or apparatus coating on selected surface areas by masking
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  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Definitions

• This disclosure relates to the fabrication of semiconductor devices, and more particularly, to a method of forming a bump structure without of under-bump metallurgy (UBM) undercut.
• UBM under-bump metallurgy
• Interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits.
• bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding.
• interconnect structures are formed on metallization layers, followed by the formation of under-bump metallurgy (UBM), and the mounting of solder balls.
• UBM under-bump metallurgy
• Flip-chip packaging utilizes bumps to establish electrical contact between a chip's I/O pads and the substrate or lead frame of the package.
• a bump actually contains the bump itself and a so-called under bump metallurgy (UBM) located between the bump and an I/O pad.
• UBM under bump metallurgy
• An UBM generally contains an adhesion layer, a barrier layer and a wetting layer, arranged in this order on the I/O pad.
• the bumps themselves based on the material used, are classified as solder bumps, gold bumps, copper pillar bumps and bumps with mixed metals.
• copper interconnect post technology is proposed. Instead of using solder bump, the electronic component is connected to a substrate by means of copper post.
• the copper interconnect post technology achieves finer pitch with minimum probability of bump bridging, reduces the capacitance load for the circuits and allows the electronic component to perform at higher frequencies.
• a solder alloy is still necessary for capping the bump structure and jointing electronic components as well.
• FIGS. 1 to 4, 4A, 4B and 5 to 7 are cross-sectional diagrams depicting an exemplary embodiment of forming a bump structure without UBM undercut;
• FIGS. 8 to 10 are cross-sectional diagrams depicting an exemplary embodiment of forming a Cu post bump structure without UBM undercut.
• This disclosure provides a bump process used in semiconductor devices having solder bumps, Cu posts, post passivation interconnects, and/or through-silicon vias (TSVs) fabricated thereon, applied to flip-chip assembly, wafer-level chip scale package (WLCSP), three-dimensional integrated circuit (3D-IC) stack, and/or any advanced package technology fields.
• TSVs through-silicon vias
• WLCSP wafer-level chip scale package
• 3D-IC three-dimensional integrated circuit
• FIGS. 1 to 7 depicting an exemplary embodiment of a method of forming a bump structure without UBM undercut.
• an example of a substrate 10 used for bump fabrication may comprise a semiconductor substrate as employed in a semiconductor integrated circuit fabrication, and integrated circuits may be formed therein and/or thereupon.
• the semiconductor substrate is defined to mean any construction comprising semiconductor materials, including, but is not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used.
• the substrate 10 may further comprise a plurality of isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. The isolation features may define and isolate the various microelectronic elements (not shown).
• STI shallow trench isolation
• LOC local oxidation of silicon
• Examples of the various microelectronic elements that may be formed in the substrate 10 include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.); resistors; diodes; capacitors; inductors; fuses; and other suitable elements.
• transistors e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.
• resistors e.g., resistors; diodes; capacitors; inductors; fuses; and other suitable elements.
• Various processes are performed to form the various microelectronic elements including deposition,
• the microelectronic elements are interconnected to form the integrated circuit device, such as a logic device, memory device (e.g., SRAM), RF device, input/output (I/O) device, system-on-chip (SoC) device, combinations thereof, and other suitable types of devices.
• a logic device e.g., SRAM
• RF device e.g., RF
• I/O input/output
• SoC system-on-chip
• the substrate 10 further includes inter-layer dielectric layers and a metallization structure overlying the integrated circuits.
• the inter-layer dielectric layers in the metallization structure include low-k dielectric materials, un-doped silicate glass (USG), silicon nitride, silicon oxynitride, or other commonly used materials.
• the dielectric constants (k value) of the low-k dielectric materials may be less than about 3.9, or less than about 2.8.
• Metal lines in the metallization structure may be formed of copper or copper alloys. One skilled in the art will realize the formation details of the metallization layers.
• a contact region 12 is a top metallization layer formed in a top-level inter-layer dielectric layer, which is a portion of conductive routs and has an exposed surface treated by a planarization process, such as chemical mechanical polishing (CMP), if necessary.
• Suitable materials for the conductive region 12 may include, but are not limited to, for example copper (Cu), aluminum (Al), AlCu, copper alloy, or other mobile conductive materials.
• the contact region 12 is a metal pad region 12 , which may be used in the bonding process to connect the integrated circuits in the respective chip to external features.
• FIG. 1 also depicts a passivation layer 14 formed on the substrate 10 and patterned to form a first opening 15 exposing a portion of the metal pad region 12 for allowing subsequent bump formation.
• the passivation layer 14 is formed of a non-organic material selected from un-doped silicate glass (USG), silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof.
• the passivation layer 14 is formed of a polymer layer, such as an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, although other relatively soft, often organic, dielectric materials can also be used.
• FIG. 1 further depicts a polymer layer 16 that is formed on the passivation layer 14 and patterned to form a second opening 17 exposing a portion of the metal pad region 12 for allowing subsequent bump formation.
• the second opening 17 may be smaller than, equal to, or greater than the first opening 15 .
• the second opening 17 is positioned within the first opening 15 .
• the polymer layer 16 is formed of a polymer, such as an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, although other relatively soft, often organic, dielectric materials can also be used.
• the polymer layer 16 is a polyimide layer.
• the polymer layer 16 is a polybenzoxazole (PBO) layer.
• PBO polybenzoxazole
• the polymer layer 16 is soft, and hence has the function of reducing inherent stresses on substrate.
• the polymer layer 16 is easily formed to thickness of tens of microns.
• first under-bump-metallurgy (UBM) layer 18 is formed on the resulting structure.
• the first UBM layer 18 is formed on the polymer layer 16 and the exposed portion of the metal pad region 12 , and lines the sidewalls and bottom of the second opening 17 .
• the first UBM layer 18 also referred to as a diffusion barrier layer, may be formed of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), or the like.
• the formation methods include physical vapor deposition (PVD) or sputtering.
• the first UBM layer 18 is deposited to a thickness of between about 500 and 2000 angstrom and more preferably to a thickness of about 1000 Angstrom.
• a mask layer 20 is provided on the first UBM layer 18 and patterned with a third opening 21 exposing a portion of the first UBM layer 18 for bump formation.
• the diameter of the third opening 21 is greater or equal to the diameter of the second opening 17 .
• the mask layer 20 is a dry film or a photoresist film through the steps of coating, curing, descum and the like, followed by lithography technology and etching processes such as a dry etch and/or a wet etch process.
• a second UBM layer 22 is selectively formed on the first UBM layer 18 within the opening 21 of the mask layer 20 through an electroless deposition.
• an electroless Cu deposition is performed to selectively plate a Cu layer on the exposed portion of the first UBM layer 18 .
• the second UBM layer 22 has a thickness about 1 ⁇ 10 um, for example about 4 ⁇ 6 um, although the thickness may be greater or smaller.
• Palladium (Pd) is often used as the activated base metal for electroless copper plating. After activation, electroless deposition of Cu occurs on the catalytic surface. In general, the coverage of the Cu deposit reaches 100% and the adsorptive amount of Pd is greatly increased by the conditioning process. However, in order to insure uniformity, the diffusion barrier layer must substantially be free of any metal oxide they may have formed prior to the electroless Cu plating process.
• FIGS. 4A and 4B depicts an exemplary embodiment of performing an electroless Cu deposition on the first UBM layer 18 .
• an activation or initiation step is performed.
• the activation or initiation step is a palladium (Pd) activation or Pd initiation.
• the pretreatments used in the Cu electroless plating process include the removal of the titanium oxide (TiO 2 ) layer 24 from the diffusion barrier layer 18 using a HF solution, and the deposition of a Pd layer 26 to activate the diffusion barrier layer 18 . Then an electroless plated Cu layer 28 on the non-uniform or rough Pd layer 26 exhibits high resistivity and RMS roughness.
• the second UBM layer 22 includes a Cu UBM layer 28 and a Pd layer 26 .
• the second UBM layer 22 is referred to as a Cu layer including Pd elements.
• the Pd element is detected at the interface between the first UBM layer 18 and the second UBM layer 28 by ICP and/or SEM-EDX.
• a solder layer 30 is then formed on the second UBM layer 22 within the opening 21 of the mask layer 20 .
• the solder layer 30 may be made of Sn, SnAg, Sn—Pb, SnAgCu (with Cu weight percentage less than 0.3%), SnAgZn, SnZn, SnBi—In, Sn—In, Sn—Au, SnPb, SnCu, SnZnIn, or SnAgSb, etc.
• the mask layer 20 is removed, exposing a portion of the first UBM layer 18 .
• the mask layer 20 is a dry film, it may be removed using an alkaline solution.
• the mask layer 20 is formed of photoresist, it may be removed using acetone, n-methyl pyrrolidone (NMP), dimethyl sulfoxide (DMSO), aminoethoxy ethanol, and the like.
• the exposed portion of the first UBM layer 18 is etched back using the solder layer 30 as a mask by a conventional wet and/or dry etching process depending on the metallurgy of the first UBM metallurgy.
• Standard reactive ion etch (RIE) procedures can be used to etch the first UBM layer 18 .
• a solder reflow process may be optionally performed on the solder layer 30 .
• the substrate 10 is then sawed and packaged onto a package substrate, or another die, with solder balls or Cu bumps mounted on a pad on the package substrate or the other die.
• the completed bump structure 32 includes the first UBM layer 18 , the second UBM layer 22 and the solder layer 30 , in which the second UBM layer 22 is a Cu layer containing Pd elements.
• this disclosure provides a method of selectively forming the second UBM layer 22 by an electroless Cu deposition process after the formation of the mask layer 20 . There is no need to perform a wet etching process on the second UBM layer 22 after stripping the mask layer 20 , thus the resulted UBM scheme has an undercut-free profile.
• FIGS. 8 to 10 are cross-sectional diagrams depicting an exemplary embodiment of forming a Cu post bump structure without UBM undercut, while explanation of the same or similar portions to the description in FIGS. 1 to 7 will be omitted.
• the opening 21 is then partially filled with a conductive material with solder wettability.
• a copper (Cu) layer 34 is formed in the opening 21 to contact the underlying second UBM layer 22 .
• the Cu layer 34 is intended to include substantially a layer including pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium.
• the formation methods may include sputtering, printing, electro plating, electroless plating, and commonly used chemical vapor deposition (CVD) methods.
• electro-chemical plating ECP
• ECP electro-chemical plating
• the thickness of the Cu layer 34 is greater than 30 um.
• the thickness of the Cu layer 34 is greater than 40 um.
• the Cu layer 34 is of about 40 ⁇ 50 um thickness, or about 40 ⁇ 70 ⁇ m thickness, although the thickness may be greater or smaller.
• the Cu layer 34 is referred to as a Cu post 34 hereinafter.
• a cap layer 40 is formed on the top surface of the Cu post 34 .
• the cap layer 36 could act as a barrier layer to prevent copper in the Cu post 34 to diffuse into bonding material, such as solder alloy, that is used to bond the substrate 10 to external features. The prevention of copper diffusion increases the reliability and bonding strength of the package.
• the cap layer 34 may include nickel, tin, tin-lead (SnPb), gold (Au), silver, palladium (Pd), In, nickel-palladium-gold (NiPdAu), nickel-gold (NiAu), other similar materials, or alloys.
• the cap layer 34 is a multi-layered structure or a single-layered structure. In some embodiments as depicted in FIG.
• the cap layer 40 includes a first cap layer 36 and a second cap layer 38 .
• the first cap layer 36 is a nickel layer with a thickness about 1 ⁇ 5 um.
• the second cap layer 38 is a solder layer or a gold (Au) layer.
• the mask layer 20 is removed, exposing a portion of the first UBM layer 18 .
• the exposed portion of the first UBM layer 18 is etched back using the Cu post 34 and the cap layer 40 as a mask by a conventional wet and/or dry etching process depending on the metallurgy of the first UBM metallurgy, as shown in FIG. 10 .
• a solder reflow process may be optionally performed depending on the material of the cap layer 40 .
• the substrate 10 is then sawed and packaged onto a package substrate, or another die, with solder balls or Cu bumps mounted on a pad on the package substrate or the other die.
• the completed bump structure 42 includes the first UBM layer 18 , the second UBM layer 22 , the Cu post 34 , and the cap layer 40 , in which the second UBM layer 22 is a Cu layer containing Pd elements.
• this disclosure provides a method of selectively forming the second UBM layer 22 by an electroless Cu deposition process after the formation of the mask layer 20 . There is no need to perform a wet etching process on the second UBM layer 22 after stripping the mask layer 20 , thus the resulted UBM scheme has an undercut-free profile.

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• 2010
  • 2010-04-16 US US12/761,863 patent/US9598772B2/en active Active
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