USRE33682E - Auto focus circuit for video camera - Google Patents

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Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
  • H04N23/60—Control of cameras or camera modules
  • H04N23/67—Focus control based on electronic image sensor signals
  • H04N23/673—Focus control based on electronic image sensor signals based on contrast or high frequency components of image signals, e.g. hill climbing method
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/04—Synchronising
  • H04N5/08—Separation of synchronising signals from picture signals

Definitions

• the present invention relates to an improvement of an auto focus circuit adopted in a video camera.
• the present invention relates to an improvement of an auto focus circuit of a system in which an input video signal is evaluated to control the movement of a focusing ring by a closed loop.
• FIG. 1 is a block diagram showing an example of such a well-known auto focus circuit for a video camera as described above.
• a luminance signal Y contained in a video signal obtained by video recording is applied to a gate circuit 1.
• the gate circuit 1 selects a luminance signal Y corresponding to the sampling area in the center of the screen region.
• a gate control circuit 2 controls an open period of the gate circuit 1 based on the output of a synchronizing separation circuit 3.
• the output of the gate circuit 1 is applied to a high-pass filter 4 for cutting off the signal lower than 100 kHz.
• the output of the filter 4 attains the maximum level in a state in which the video camera is focused.
• the output of the high-pass filter 4 is supplied to an absolute value calculating circuit 5 and then it is integrated for each field in an average value calculating circuit 6.
• the integrated average value output is converted to a digital signal with a cycle of one field in an analog-to-digital (A-D) converting circuit 7.
• the converted output is written in a first memory circuit 8 and then written in a second memory circuit 9 after one field.
• the writing in the first memory circuit 8 and the second memory circuit is controlled by a vertical synchronizing signal V from the synchronizing separation circuit 3.
• the output of the first memory circuit 8 and the output of the second memory circuit 9 are compared in a comparing circuit 10 and the output of comparison is supplied to a focusing motor control circuit 11.
• the focusing motor control circuit 11 rotates in an initialized state, a focusing motor (not shown) in a predetermined direction and the rotation in this direction is maintained as far as the output of the first memory circuit 8 is larger than the output of the second memory circuit 9.
• the focusing motor is controlled to route in the opposite direction.
• the focusing motor is controlled so that the average level of the high frequency component contained in the luminance signal is always maximum.
• the average level is considerably changed dependent on the scene to be recorded. More specifically stated, the average output for recorded a scene where there is a considerable change of the luminance in the horizontal direction is ten times as large as the average output for recording a scene where there is little change of the luminance in the horizontal direction. As a result, it is difficult to determine an A-D conversion range for the average output the value of which increases or decreases considerably. Accordingly, if the A-D conversion range is adapted for a high average output, the resolution for a low average output is decreased and the function of response for control is deteriorated. On the contrary, if the A-D conversion range is adapted for a low average level, a saturation of the conversion range with respect to a high average output becomes a problem.
• the A-D conversion range is adapted for a low average value output and an average value output level exceeding the A-D conversion range is detected by a saturation level detecting circuit 12 so that the output of the gate control circuit 2 is controlled.
• scanning lines in the sampling area are decreased by every other line, every two lines, every three lines, etc. so that the average output is not saturated.
• sampling intervals are made less frequent.
• erroneous operation might occur in focusing.
• An object of the present invention is to provide an auto focus circuit for a video camera, capable of focusing with high precision without being influenced by the environmental conditions for video recording, in other words, irrespective of the change in the luminance of an object to be recorded.
• the present invention is an auto focus circuit for a video camera, in which a change in the absolute value output of a high frequency component of a luminance signal in the sampling area for focusing is converted directly to a digital amount and the averaging of the signal is performed by digital processing.
• the averaging of the high frequency component of the luminance signal is digitally performed and as compared with the case of analog processing for averaging the signal, the operation is stable. Consequently, the focusing precision based on the averaged signal is improved.
• an address circuit and a memory circuit by an integrating circuit comprising an addition circuit and a latch circuit, an auto focus circuit of a simple structure having a small storage capacity can be obtained.
• FIG. 1 is a block diagram showing an example of a conventional auto focus circuit for a video camera.
• FIG. 2 is a block diagram showing an auto focus circuit of the first embodiment of the present invention.
• FIG. 3 is a block diagram showing an auto focus circuit of the second embodiment of the present invention.
• FIG. 2 is a block diagram of an auto focus circuit of the first preferred embodiment of the present invention.
• a luminance signal Y contained in a video signal obtained by recording is supplied to a high-pass filter 4.
• a high frequency component higher than 100 kHz is separated from the luminance signal.
• separated high frequency component is supplied to an absolute value calculating circuit 5.
• an absolute value of the signal is obtained and the absolute value output is supplied to an envelope detecting circuit 13.
• an envelope of the absolute value output is detected.
• the detected output is supplied to an analog-to-digital (A-D) converting circuit 7.
• the A-D converting circuit 7 converts the received analog envelope detection signal to a digital signal during a predetermined period. Now, in the following, this period for conversion will be described.
• a pulse generating circuit 14 generates a pulse signal of 5 MHz and the pulse signal is supplied to the A-D converting circuit 7 through a gate circuit 1.
• the A-D converting circuit 7 performs digital conversion of the input signal in synchronism with the applied pulse signal only in a period in which the pulse signal is applied thereto from the gate circuit 1.
• Control of the opening and closing of the gate circuit 1 is made by a gate control circuit 2.
• the gate control circuit 2 controls the gate circuit 1 so that the gate circuit 1 is opened only in a period corresponding to a predetermined sampling area in the screen region. More specifically, the sampling area is defined by a range from 1/4 to 3/4 of a dimension of the screen region in the horizontal direction and a range from 1/4 to 3/4 of a dimension of the screen region in the vertical direction and control is made to open the gate circuit 1 only in the period corresponding to the above described sampling area.
• a horizontal synchronizing signal H and a vertical synchronizing signal V separated from the input luminance signal Y by the synchronizing separation circuit 3 are supplied as a control input for determining the sampling area.
• the pulse signal from the pulse generating circuit 14 may be applied to the gate control circuit 2 for determining the sampling area. (The line for applying the pulse signal is not shown.)
• the digital signal of eight bits for example, converted by the A-D converting circuit 7 is supplied to a memory circuit 16.
• the writing in the memory circuit 16 is controlled by an address signal generating circuit 15 using the output of the gate circuit 1 as a count input.
• the digital signal from the A-D converting circuit 7 is written successively in a prescribed area in the memory circuit 16 according to the output of the address signal generating circuit 15.
• the output of the memory circuit 16 is applied to a calculating circuit 17.
• the calculating circuit 17 adds all the digital signal values in the sampling area in one field. Then, the output of calculation obtained by the addition is first stored in a first memory 8 and then transferred to a second memory 9 in the subsequent field.
• the writting in the first memory 8 and the second memory 9 is controlled by the vertical synchronizing signal V provided from the synchronizing separation circuit 3 so that the writing is performed for each field.
• the writing in the first memory 8 and the second memory 9 is controlled by the divided vertical synchronizing signal provided from a frequency divider (not shown) so that the writing is performed for each predetermined period, for example, 1/2 field, 2 fields etc.
• a comparing circuit 10 receiving both of the output of the first memory 8 and the output of the second memory 9 compares the added value in one field and the added value in the subsequent field in the sampling area. Then, the output of .Iadd.the .Iaddend.comparison is supplied to a focusing motor control circuit 11.
• the focusing motor control circuit 11 .[.rotates in an initialized state.]. .Iadd.causes .Iaddend.the focusing motor .Iadd.(.Iaddend.not shown.Iadd.) .Iaddend.in .Iadd.an initialized state to rotate in .Iaddend.a predetermined direction.
• the rotation in the above stated direction is continued as .[.far.]. .Iadd.long .Iaddend.as the output of the second memory 9 is smaller than the output of the first memory 8.
• the focusing motor control circuit 11 reverses the rotating direction of the focusing motor.
• the focusing ring (not shown) is always moved to a position in focus.
• FIG. 3 is a block diagram of an auto focus circuit of the second preferred embodiment of the present invention.
• a luminance signal Y contained in a video signal obtained by recording is supplied to a high-pass filter 4.
• a high frequency component higher than 100 kHz is separated from the luminance signal.
• the separated high frequency component is supplied to an absolute value calculating circuit 5.
• an absolute value of the signal is obtained and the absolute value output is supplied to an envelope detecting circuit 13.
• an envelope of the absolute value output is detected.
• the detected output is supplied to an analog-to-digital (A-D) converting circuit 7.
• the A-D converting circuit 7 converts the received analog envelope detection signal to a digital signal during a predetermined period.
• the luminance signal Y is also supplied to a synchronizing separation circuit 3.
• a horizontal synchronizing signal H and a vertical synchronizing signal V are separated from the luminance signal Y.
• the separated horizontal synchronizing signal H and vertical synchronizing signal V are supplied to a gate control circuit 2.
• the gate control circuit 2 controls a gate circuit 1 so that the gate circuit 1 is opened only in a period corresponding to a predetermined sampling area in the screen region. More specifically, the sampling area is defined by a range from 1/4 to 3/4 of a dimension of the screen region in the horizontal direction and a range from 1/4 to 3/4 of a dimension of the screen region in the vertical direction and the opening of the gate circuit 1 is controlled so that the signal in the sampling area is extracted.
• the sampling area is not limited to the area as defined above and may be an arbitrary region in the screen region. Otherwise, the sampling area may be variable by selecting operation.
• a pulse signal of 5 MHz is supplied from a pulse generating circuit 14.
• the pulse signal of 5 MHz is supplied to the A-D converting circuit 7 in a period in which the gate circuit 1 is opened by the gate control circuit 2, and with the timing of the pulse signal, the analog envelope detecting signal is converted to a digital signal of eight bits for example.
• the pulse signal provided from the gate circuit 1 is supplied as a latch pulse to a latch circuit 12b in an integrating circuit 12 to be described later.
• the pulse signal from the pulse generating circuit 14 may be applied to the gate control circuit 2 for determining the sampling area.
• the integrating circuit 12 comprises an addition circuit 12a and a latch circuit 12b.
• the addition circuit 12a has a closed loop structure in which the digital signal provided from the A-D converting circuit 7 and the digital signal provided from the latch circuit 12b are added and the output of addition is supplied to the latch circuit 12b.
• the latch circuit 12b latches the input signal according to the latch pulse supplied from the above stated gate circuit 1.
• the latch circuit 12b is reset by the vertical synchronizing signal V supplied from the synchronizing separation circuit 3.
• the latch circuit 12b integrates the output of the A-D converting circuit 7 by a field cycle.
• first memory 8 is connected on .Iaddend.the output side of the latch circuit 12b, .[.a first memory 8 is connected.]. and .Iadd.a second memory 9 is connected .Iaddend.to the first memory 8.[., a second memory 9 is connected.]..
• Both of the memories 8 and 9 are controlled by the vertical synchronizing signal V so that writing operation is performed in the memories 8 and 9.
• the memories 8 and 9 provide the signals stored at present as .[.far.]. .Iadd.long .Iaddend.as new data is not written.
• These first memory 8 and second memory 9 are formed by D-flip-flops for example.
• the resetting on the latch circuit 12b and the writting of the first memory 8 and the second memory 9 are controlled in synchronism with the vertical synchronizing signal V. Accordingly, for each field, the content of the latch circuit 12b is written in the first memory 8 and with a delay of one field, the content is written in the second memory 9.
• a divided vertical synchronizing signal can be used as a control signal. In such a case, for each predetermined period, for example, 1/2 field or 2 fields etc. the content of the latch circuit 12b is written in the first memory 8 and, with a delay of one predetermined period, the content is written in the second memory 9.
• a comparing circuit 10 receiving the output of the first memory 8 and the output of the second memory 9 compares by a field cycle, the digital converted data in one field (this data being supplied from the second memory 9) and the digital converted data in the field coming one field .[.ahead of.]. .Iadd.behind .Iaddend.the above stated field (this data being supplied from the first memory 8) and the output of comparison is supplied to a focusing motor control circuit 11.
• the focusing motor control circuit 11 controls the focusing motor in the same manner as in the first embodiment and the prior art so that the most suitable focusing operation is performed.
• processing of the signal after A-D conversion that is, addition, writing and other processing of the digital signal are performed with predetermined timing based on the vertical synchronizing signal V separated from the luminance signal Y.
• processing of the digital signal can be performed using software, in other words, a microcomputer provided with a program for desired operation.

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• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Theoretical Computer Science (AREA)
• Automatic Focus Adjustment (AREA)

Abstract

Description

Claims (9)

Applications Claiming Priority (2)

Related Parent Applications (1)

Publications (1)

Family

ID=16874402

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Cited By (57)

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Citations (13)

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• 1984
  • 1984-10-30 JP JP59228308A patent/JPS61105978A/en active Pending
• 1985
  • 1985-10-28 US US06/791,843 patent/US4638364A/en not_active Ceased
  • 1985-10-29 DE DE8585113714T patent/DE3575254D1/en not_active Expired - Lifetime
  • 1985-10-29 KR KR1019850007995A patent/KR920009068B1/en not_active IP Right Cessation
  • 1985-10-29 EP EP85113714A patent/EP0180186B1/en not_active Expired - Lifetime
• 1989
  • 1989-01-19 US US07/299,189 patent/USRE33682E/en not_active Expired - Lifetime

Patent Citations (13)

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