USRE40976E1 - Common source EEPROM and flash memory - Google Patents

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• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
  • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
  • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor

Definitions

• the present invention relates to semiconductor nonvolatile memories. More particularly, the present invention relates to an improved EEPROM and flash memories.
• nonvolatile memory cells have been used in commercial products for many years, ranging from EPROM to EEPROM and Flash memories. See, for example, “IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays” IEEE Std 1005-1998. The cited reference provides a good background of the various types of memory devices that have been produced and provide a list of the terms used in this disclosure.
• EPROM and Flash memories usually employ a single MOS transistor with two gates stacked on top of each other, the floating gate and the control gate, and the conductive state of the transistor can be changed by injecting electrons onto or removing electrons from the floating gate.
• EEPROM (byte erasable) memories usually are fabricated with separate select and control gate (such as the FLOTOX cell), although there are examples of products where a split gate is also used.
• the non selected memory transistors belonging to the selected bitline and which have been programmed to a conductive state they conduct current even if abs(Vgs) ⁇ 0) cannot be changed to a nonconductive during the read mode unless the voltage of the non selected wordlines can be set to be below V ss (for NMOS cells) or about V cc (for PMOS cells). Generation of these voltages complicates the design of the memories.
• leakage current an uncontrolled amount of current flows through the selected bitline and the common source, making the correct reading of the state of the selected memory transistor very difficult.
• This problem has been lessened by insuring that the memory transistor is never erased (for a NMOS cell) or programmed (for a PMOS cell) to a normally on state when the gate-source voltage is zero, or by adding the select gate to the memory transistor (split gate cell).
• a normally on MOS device is often called a depletion device.
• drain turn-on Another problem with a conventional array using a stacked gate cell and a common source is referred to as a “drain turn-on” problem.
• a drain turn-on problem As an example, in an array utilizing a NMOS memory cell, applying 6 V on the drain (the bitline) and 9 V on the wordline does the programming of the selected cell.
• the wordline of the non-selected rows is kept at V ss , but the drains of all the cells connected to the selected bitline are biased at 6 V.
• the capacitive coupling between the drain and the wordline will bring the potential of the floating gate to value comprised between 0 and 6 V.
• the actual value depends on the geometry of the cell and can be easily such that the non-selected cells are turned on. In this case each non-selected cell on the selected bitline is going to draw current and the total amount of current required for programming is increased.
• a nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors.
• the sources of the memory cell transistors in each row of the array are electrically coupled together.
• the control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row.
• the drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column.
• a source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the source of all memory cell transistors in that row, and a gate coupled to the wordline.
• an array of split-gate nonvolatile memory cell is provided.
• the array is arranged as a plurality of rows and columns of split-gate memory cell transistors.
• the sources of the split-gate memory cell transistors in each pair of adjacent rows of the array are electrically coupled together.
• the control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row.
• the drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column.
• a source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline.
• FIG. 1 is an electrical schematic diagram of a stacked memory array according to the present invention.
• FIG. 2 is a diagram showing an illustrative layout for the array of FIG. 1 .
• FIG. 3 is an electrical schematic diagram of a second memory array according to the present invention.
• FIG. 4 is a diagram showing an illustrative layout for the array of FIG. 3 .
• FIG. 5 is an electrical schematic diagram of an array employing a split gate cell.
• FIG. 6 is a diagram showing an illustrative layout for the array of FIG. 5 .
• FIG. 7 is an electrical schematic diagram of an illustrative one-time-programmable memory array according to the present invention.
• FIGS. 8A through 8C are layout diagrams providing comparisons of memory cells according to the present invention with a prior-art memory cell.
• the memory array configurations described herein completely eliminate the current leakage problem and the drain turn-on problem associated with prior-art memory arrays.
• the memory transistors can be programmed or erased without restrictions on the threshold voltage (the memory transistor can be set to operate as a depletion device) or the drain coupling ratio. This improves the cell read current for a given set of biasing condition during read, as compared to the case where the memory cell cannot be set to operate as a depletion device. This translates into a reduced read access time, or, for a given cell current, it allows the use of a lower power supply voltage.
• the memory array configurations disclosed herein can employ either NMOS or PMOS memory cells of the stacked or split gate type.
• the memory cells disclosed herein use well-proven mechanisms for programming and erasing the cells. All of the array configurations can be used for implementing Flash memories organized in sectors or full-function EEPROM memories organized in bytes.
• One array configuration will be shown which can be used for implementing single poly EPROM function using a simple PMOS transistor as the memory element.
• FIG. 1 is an electrical schematic diagram of the memory array of the nonvolatile memory cell array 10 .
• the nonvolatile memory cell array 10 of FIG. 1 is made of NMOS single transistor memory cells including a nonvolatile memory transistor 11 . These memory cells are similar to the ETOX cell developed by Intel.
• Each nonvolatile memory transistor 11 has a source 12 , a drain 13 , a floating gate 14 , and a control gate 15 .
• Wordlines W 0 , W 1 , . . . W 2n , W 2n+1 are used to select half of a given row of nonvolatile memory transistors 11 of the nonvolatile memory cell array 10 .
• Each of the wordlines W 0 , W 1 , . . . W 2n , W 2n+1 activates a row of control gates 15 .
• Bitlines, B 0,0 , B 0,1 . . . B 0,7 are used to select of a given column of nonvolatile memory transistors 11 of the nonvolatile memory cell array 10 .
• Source, S is used to select the N+ source diffusion common to each row of nonvolatile memory transistors 11 . This is different from a typical ETOX array where the sources of two adjacent rows of transistors are merged.
• Each row of NMOS single transistor memory cells 11 of the nonvolatile memory cell array 10 has a source select transistors T 0 , T 1 , . . . T 2n , T 2n+ associated with it.
• the source select transistors T 0 , T 1 , . . . T 2n , T 2n+1 selects the N+ diffusion common for a row of NMOS single transistor memory cells 11 .
• T 2n , T 2n+1 source 16 is connect to the source S and the drain is connect to the row of nonvolatile memory transistor's 11 source 12 .
• Each source select transistors T 0 , T 1 , . . . T 2n , T 2n+1 control gate 17 is activated by the Wordlines W 0 , W 1 , . . . W 2n , W 2n+1 .
• Each memory byte of NMOS single transistor memory cell nonvolatile memory transistors 11 of the nonvolatile memory cell array 10 are isolated within a P-well PW 0 , PW 1 . . . PW n creating a well contained memory byte 19 .
• the P-well can be biased to the appropriate P-well voltage V pw , by using, for instance, the CMOS inverter 18 .
• the CMOS inverter selects the P-well PW 0 , PW 1 , . . . PW n via the CMOS inverter gate V gpw0 , V gpw1 , . . . V n activated to Vcc.
• the floating gate 14 of the array nonvolatile memory transistors 11 in nonvolatile memory cell array 10 is the memory cell.
• the erasure, programming and reading of the floating gate 14 of the NMOS single transistor memory cells 11 in nonvolatile memory cell array 10 is the memory cell voltages as indicated in Table 1.
• the values of the voltages indicated in Table 1 are typical of the type of cell, but they may vary depending on the process technology and the geometry of the cell.
• the floating gate 14 (memory cell 0,0) is programmed when wordline W 0 is at +9 volts, with the rest of the wordlines W 1 , . . . W 2n , W 2n+1 at 0 volts; and the bitline B 0 is at +6 volts, with the rest of the bitlines B 0,0 , B 0,1 . . . B 0,7 at 0 volts.
• Source is at 0 volts, V gpw0-n at Vcc, and V pw at 0 volts.
• the floating gate 14 (memory cell 0,0) is selectively programmed by Channel Hot Electrons (CHE) injected into the floating gate 14 (memory cell 0,0) using the conditions mentioned above and the threshold is raised to a positive value safely above Vcc.
• CHE Channel Hot Electrons
• FIG. 2 is an illustrative layout of the memory array of the nonvolatile memory cell array 10 of FIG. 1 .
• the nonvolatile memory cell array 20 of FIG. 2 is made of NMOS single transistor memory cells or nonvolatile memory transistors 21 . These memory cells are similar to the ETOX cell developed by Intel.
• Each nonvolatile memory transistor 21 has a source 22 , a drain 23 , a floating gate 24 , and a control gate 25 .
• Wordlines W 0 , W 1 , . . . W 2n , W 2n+1 are used to select half of a given row of nonvolatile memory transistors 21 of the nonvolatile memory cell array 20 .
• Each of the wordlines W 0 , W 1 , . . . W 2n , W 2n+1 activates a row of control gates 25 .
• Bitlines, B 0,0 , B 0,1 . . . B 0,7 are used to select of a given column of nonvolatile memory transistors 21 of the nonvolatile memory cell array 20 .
• Each of the bitlines, B 0,0 , B 0,1 . . . B 0,7 connected to a column of drains 23 via the contact 26 .
• Source S is used to select the N+ source diffusion common to each row of nonvolatile memory transistors 21 . This is different from a typical ETOX array where the sources of two adjacent rows of transistors are merged.
• the floating gate 24 of the array nonvolatile memory transistors 21 in nonvolatile memory cell array 20 is the memory cell.
• the erasure, programming and reading of the floating gate 24 of the nonvolatile memory transistors 21 in nonvolatile memory cell array 20 is the memory cell voltages as indicated in Table 1.
• the values of the voltages indicated in Table 1 are typical of the type of cell, but they may vary depending on the process technology and the geometry of the cell.
• the nonvolatile memory cell array 10 shown in FIG. 1 is a stacked P-well selected single nonvolatile memory cell addressable array. Additional columns of source select transistors T 0 , T 1 , . . . T 2n , T 2n+1 can be introduced in the array in order to keep the resistance of the source diffusion within acceptable limits creating a group of well contained memory bytes 19 . Multiple columns of source selection transistors will require separate addressing not depicted but well known in the art.
• V ss shown as the bottom rail indicates the lowest voltage supplied externally and in the following is considered equal to the group potential.
• V cc indicates the operating voltage of the circuit.
• the N+ source diffusion is common to each row of nonvolatile memory transistors 11 . This is different from a typical prior-art ETOX array where the sources of two adjacent rows of transistors are merged.
• the source of each row 12 is connected to the drain 12 of the source select transistors T 0 , T 1 , . . . T 2n , T 2n+1 .
• the gate of the source select transistors T 0 , T 1 , . . . T 2n , T 2n+1 of one row is the same as the wordline W 0 , W 1 , . . . W 2n , W 2n+1 of the row.
• the novel nonvolatile memory cell array 10 configuration described substantially eliminates the current leakage and drain turn-on problem, and the memory transistors can be programmed or erased without restriction on the threshold voltage or the drain coupling ratio.
• the memory transistor can be set to operate as a depletion device. This improves the cell read current for a given set of biasing condition during read, as compared to the case where the memory cell cannot be set to operate as a depletion device. This translates into a reduced read access time, or, for a given cell current, it allows the use of a lower power supply voltage.
• erase is the nonselective operation since all the cells of one byte 19 (byte erase) or on the entire selected row (sector erase) are erased. It is also assumed, as it is customarily done in Flash or EEPROM arrays with NMOS memory cells, that the programming operation is always preceded by the erase operation.
• Erasing the nonvolatile memory cell occurs as a result of Fowler-Nordheim (FN) tunneling of electrons from the floating gate 14 in FIG. 1 and 24 in FIG. 2 to the P-well PW 0 , PW 1 , . . . PW n .
• This type of erase is usually called uniform channel erase and is preferred to the other two mechanism which have been used, source erase or negative gate source erase. These other erase mechanisms create a significant band-to-band tunneling current. Band-to-band tunneling current has two deleterious effects; it increases the amount of current needed for erasing the byte/sector 19 , and it also may create retention problems caused by injection of hot holes into the floating gate.
• Channel erase can be used in this array because a floating P-Well PW 0 , PW 1 , . . . PW n is used which can be biased positively respect to ground. This well configuration is often called Triple Well.
• Reading of the nonvolatile memory cell is performed under the conditions defined in Table 1.
• the source select transistor T 0 , T 1 , . . . T 2n , T 2n+1 which is a NMOS transistor designed to be an enhancement type, is turned on, bringing the voltage of the common source of the cells of that row to a potential close to ground.
• the array configuration of FIGS. 1 and 2 has the advantage that the erased threshold can be set to a convenient negative value, since, during reading of the selected cell, the other nonvolatile memory cells connected to the selected bitline B 0,0 , B 0,1 , . . . B 0,7 , irrespective of their state, cannot contribute any current because their sources are floating.
• the penalty for using this cell as compared to the other arrays is a small increase of the vertical dimension of the nonvolatile memory cell, as it will be shown later.
• the worst-case maximum voltage that the memory transistor has to sustain is +6 V on the drain side 13 in FIG. 1 and 23 in FIG. 2 with the wordline W 0 , W 1 , . . . W 2n , W 2n+1 grounded (unselected nonvolatile memory cells on the selected bitline B 0,0 , B 0,1 , . . . B 0,7 ).
• the source select transistor T 0 , T 1 , . . . T 2n , T 2n+1 has to be able to sustain reliably +/ ⁇ 9 V between the gate and the source, drain and body terminals.
• the maximum field across the gate oxide has to be kept below 6 mV/cm, which requires a gate oxide thickness of ⁇ 150 A.
• the voltage on the junctions of these transistors is limited to 6 V.
• the well-select CMOS transistors 18 have to sustain +7 V between any terminals. Therefore, in addition to the memory device, enhancement type CMOS devices with ⁇ 150 A gate oxide need to be available for the source select transistor T 0 , T 1 , . . . T 2n , T 2n+1 and for switching the P-wells PW 0 , PW 1 , . . . PW n .
• the voltages, which the junctions have to sustain, are below 10 V and these sustaining voltages can be obtained with the junction usually formed for making logic CMOS devices down to 0.25 um technologies.
• the process flow outlined below assumes that the nonvolatile memory cell array and the peripheral circuits are embedded in a digital product made with a conventional CMOS process used for digital products (hereinafter the “Logic Process”), to which the process steps required by the nonvolatile memory cell transistors and the high voltage devices are added.
• CMOS process used for digital products
• the Logic Process employs the so-called retrograde well approach as first introduced in the 0.35 um technology node and bulk P-type starting material is used.
• retrograde wells it is very difficult to use the logic retrograde wells for the nonvolatile devices because of the different requirements for threshold voltages and maintaining voltages. It is therefore assumed that the logic wells and the wells used for the nonvolatile memory cell devices are different.
• a memory byte 19 is separated by P-Wells PW 0 , PW 1 , . . . PW n with memory byte 19 selection being accomplished by using a CMOS inverter 18 .
• memory byte 39 selection is accomplished using a multiple of source selection S 0 , . . . S n replacing the need for the P-wells PW 0 , PW 1 , . . . PW n of FIG. 1 .
• the multiple source selection nonvolatile memory cell array 30 of FIG. 3 is made of nonvolatile memory transistors 31 .
• the multiple of source selection S 0 . . . S n are used for memory byte 39 or sector selection.
• the entire array can be placed on a common well which does not have to be electrically isolated from the substrate.
• FIG. 3 is an electrical schematic diagram of the multiple source selection nonvolatile memory cell array 30 .
• Each nonvolatile memory transistors 31 has a source 32 , a drain 33 , a floating gate 34 , and a control gate 35 .
• Wordlines W 0 , W 1 , . . . W 2n , W 2+1 are used to select half of a given row of nonvolatile memory transistors 31 of the multiple source selection nonvolatile memory cell array 30 .
• Each of the wordlines W 0 , W 1 , . . . W 2n , W 2n+1 activates a row of control gates 35 .
• Bitlines, B 0,0 , B 0,1 . . . B 0,7 are used to select of a given column of nonvolatile memory transistors 31 of the multiple source selection nonvolatile memory cell array 30 .
• the multiple of source selection S 0 . . . S n are used to select the N+ source diffusion common to each row of nonvolatile memory transistors 31 . This is different from a typical ETOX array where the sources of two adjacent rows of transistors are merged.
• Each row of nonvolatile memory transistors 31 for each memory byte 39 of the multiple source selection nonvolatile memory cell array 30 has a source select transistors T 0,0 , T 0,1 . . . T n,0 , n,2n+1 associated with it.
• T n,0 , T n,2n+1 selects the N+ diffusion common for a row of NMOS single transistor memory cells 31 for each memory byte 39 .
• the source select transistors T 0,0 , T 0,1 , . . . , T n,0 , T n,2n+1 source 36 is connect to the multiple source selection S 0 . . . S n and the drain is connect to the row of nonvolatile memory transistor's 31 source 32 .
• Each source select transistors T 0,0 , T 0,1 , . . . T n,0 , T n,2n+1 control gate 37 is activated by the Wordlines W 0 , W 1 , . . . W 2n , W 2n+1 .
• Each memory byte 39 of nonvolatile memory transistors 31 of the multiple source selection nonvolatile memory cell array 30 are isolated by the multiple source selection S 0 . . . S n .
• the floating gate 34 of the array NMOS single transistor memory cells 31 in multiple source selection nonvolatile memory cell array 30 is the memory cell.
• the erasure, programming and reading of the floating gate 34 of the nonvolatile memory transistors 31 in the multiple source selection nonvolatile memory cell array 30 is the memory cell voltage as indicate in Table 2.
• the values of the voltages indicated in Table 2 are typical of the type of cell, but they may vary depending on the process technology and the geometry of the cell.
• the floating gate 34 (memory cell 0,0,0 S 0 , W 0 , B 0,0 ) is programmed when wordline W 0 is at +9 volts, with the rest of the wordlines W 0 . . . W 2n , W 2n+1 at 0 volts and the bitline B 0,0 is at +6 volts, with the rest of the bitlines B 0,0 , . . . B 0,7 at 0 volts, multiple source selection S 0 is at 0 volts and the rest of the multiple source selection S 0 . . . S n float.
• the floating gate 34 (memory cell 0,0,0) is selectively programmed by Channel Hot Electrons (CHE) injected into the floating gate 34 (memory cell 0,0,0) using the conditions mentioned above and the threshold is raised to a positive value safely above V cc .
• CHE Channel Hot Electrons
• FIG. 4 is an illustrative layout of the multiple source selection nonvolatile memory cell array 40 of FIG. 3 .
• the multiple source selection nonvolatile memory cell array 40 of FIG. 4 is made of NMOS single transistor memory cells 41 .
• the circuit of FIG. 4 is similar to circuit of FIG. 2 with the differences note below.
• the multiple of source selection S 0 . . . S n are used to select the N+ source diffusion common to each row of NMOS single transistor memory cells 41 . This is different from a typical ETOX array where the sources of two adjacent rows of transistors are merged.
• Each row of NMOS single transistor memory cells 41 for each memory byte 49 of the multiple source selection nonvolatile memory cell array 40 has a source select transistors T 0,0 , . . . T 0,1 , T n,0 , T n,2+1 , associated with it.
• the source select transistors T 0,0 , T 0,1 , . . . T n,0 , T n,2n+1 selects the N+ diffusion common for a row of NMOS single transistor memory cells 41 for each memory byte 49 .
• Each memory byte 49 of nonvolatile memory transistors 41 of the multiple source selection nonvolatile memory cell array 40 are isolated by the multiple source selection S 0 . . . S n .
• the novel multiple source selection nonvolatile memory cell array 40 configuration described herein substantially eliminates the current leakage and drain turn-on problem, and the memory transistors can be programmed or erased without restrictions on the threshold voltage or the drain coupling ratio.
• the memory transistor can be set to operate as a depletion device. This improves the cell read current for a given set of biasing condition during read, as compared to the case where the memory cell cannot be set to operate as a depletion device. This translates into a reduced read access time and/or for a given cell current, it allows the use of a lower power supply voltage.
• erase is the non-selective operation since all the cells of one byte (byte erase) or on the entire selected row (sector erase) are erased. It is also assumed, as it is customary in Flash or EEPROM arrays with NMOS memory cells, that the programming operation is always preceded by the erase operation.
• Erase of the cell occurs as a result of FN tunneling from the floating gate to the source.
• This type of erase is done using the so-called grounded gate source erase mechanism, which has been widely used for Flash memories.
• V s+ indicates a voltage slightly above the threshold of the source select transistor.
• This type of erase has several drawbacks, as mentioned before.
• a dedicated source junction has to be fabricated which complicates the process.
• Reading of the cell is done under the conditions defined in Table 2. Again it is clear that no leakage current problem exist during reading because the source select transistor of the mirrored cell is off. As a result the erased threshold of this cell can be set negative.
• the array described with reference to FIGS. 3 and 4 does not require isolated P-Wells, which simplifies the process. Due to the lack of a P-well for the source junctions as in FIG. 1 , a specially designed source junction is used.
• the junction is a grounded gate source array mechanism as well known in the art and is an IEEE standard.
• FIG. 5 the electrical schematic diagram of a split gate nonvolatile memory cell array 50 .
• the split gate nonvolatile memory cell array 50 circuit depicted in FIG. 5 is similar to the nonvolatile memory cell array 10 circuit depicted in FIG. 1 with the differences note below.
• Split gate nonvolatile memory cell array 50 is made of split gate nonvolatile memory transistors 51 .
• Each split gate nonvolatile memory transistor 51 has a source 52 , a drain 53 , a floating gate 54 , and a control gate 55 .
• Wordlines W 0 , W 1 , . . . W 2n , W 2n+1 overlap the floating gate 54 on two sides or one side only (as shown later in FIG. 8c , split gate memory cell layout).
• the operation of the wordline over the diffusion area is called the memory select 69 or FIG. 6 .
• Each of the wordlines W 0 , W 1 . . . W 2n , W 2n+1 activates a row of control gates 55 .
• Source, S is used to select the N+ source diffusion common to each row of split gate nonvolatile memory transistor 51 .
• Each row of split gate nonvolatile memory transistor 51 of the split nonvolatile memory cell array 50 has a source select transistors T 0 , T 1 , . . . T 2n , T 2n+1 , associated with it.
• the source select transistors T 0 , T 1 , . . . T 2n , T 2n+1 selects the N+ diffusion common for a row of split gate nonvolatile memory transistor 51 .
• T 2n , T 2+1 source 56 is connect to the source S and the drain is connect to both mirrored rows of split gate nonvolatile memory transistors 51 source 52 .
• Each source select transistors T 0 , T 1 , . . . T 2n , T 2n+1 control gate 57 is activated by the wordlines W 0 , W 1 , . . . W 2n , W 2n+1 .
• the N+ source diffusion is now shared by two rows of mirrored split gate nonvolatile memory transistors 51 and is connected to one side of the source select transistors T 0 , T 1 , . . . T 2n , T 2n+1 .
• This saving in cell height is compensated by the need to have a wider wordline on the memory cell.
• the definition of the wordlines of the memory cells can be done with the patterning step of the logic gates and the complex patterning step of the stacked gate is avoided.
• the floating gate 54 of the array split gate nonvolatile memory transistor 51 in split gate nonvolatile memory cell array 50 is the memory cell.
• the erasure, programming and reading of the floating gate 54 of the split gate nonvolatile memory transistor 51 in split gate nonvolatile memory cell array 50 is the memory cell voltages as indicate in Table 3.
• the values of the voltages indicated in Table 3 are typical of the type of cell, but they may vary depending on the process technology and the geometry of the cell.
• the floating gate 54 (memory cell 0,0) is programmed when wordline W 0 is at +9 volts, with the rest of the wordlines W 1 , . . .
• the floating gate 54 (memory cell 0,0) is selectively programmed by Channel Hot Electrons (CHE) injected into the floating gate 54 (memory cell 0,0) using the conditions mentioned above and the threshold is raised to a positive value safely above Vcc.
• CHE Channel Hot Electrons
• FIG. 6 is an illustrative layout of the memory array of the split gate nonvolatile memory cell array 50 of FIG. 5 .
• the split gate nonvolatile memory cell array 60 of FIG. 6 is made of split gate NMOS single transistor memory cells or split gate nonvolatile memory transistors 61 .
• the split gate nonvolatile memory cell array 60 circuit depicted in FIG. 6 is similar to the nonvolatile memory cell array 20 circuit depicted in FIG. 2 with the differences note below.
• the split gate nonvolatile memory cell array 60 is made of split gate nonvolatile memory transistors 61 .
• Each split gate nonvolatile memory transistor 61 has a source 62 , a drain 63 , a floating gate 64 , and a control gate 65 .
• Wordlines W 0 , W 1 , . . . W 2n , W 2n+1 overlap the floating gate 64 on two sides or one side only (as shown later in FIG. 8c , split gate memory cell layout).
• the portion of the wordline over the diffusion area is called the memory select 69 .
• Each of the wordlines W 0 , W 1 , . . . W 2n , W 2n+1 activates a row of control gates 65 .
• the N+ source diffusion is now shared by two rows of mirrored split gate nonvolatile memory transistor 61 and is connected to one side of the source 62 . This saving in cell height is compensated by the need to have a wider wordline on the memory cell.
• the definition of the wordlines of the memory cells can be done with the patterning step of the logic gates and the complex patterning step of the stacked gate is avoided.
• the floating gate 64 of the array of split gate nonvolatile memory transistors 61 in split gate nonvolatile memory cell array 60 is the memory cell.
• the erasure, programming and reading of the floating gate 64 of the split gate nonvolatile memory transistors 61 in split gate nonvolatile memory cell array 60 is the memory cell voltages as indicate in Table 3.
• the novel split gate nonvolatile memory cell array 60 configuration described completely eliminates the current leakage problem and the drain turn-on problem and the memory transistors can be programmed or erased without restrictions on the threshold voltage or the drain coupling ratio.
• the memory transistor can be set to operate as a depletion device. This improves the cell read current for a given set of biasing condition during read, as compared to the case where the memory cell cannot be set to operate as a depletion device. This translates into a reduced read access time, or, for a given cell current, it allows the use of a lower power supply voltage.
• erase is the non-selective operation since all the cells of one byte (byte erase) or on the entire selected row (sector erase) are erased. It is also assumed, as it is customarily done in Flash or EEPROM arrays with NMOS memory cells, that the programming operation is always preceded by the erase operation.
• Erase of the cell (removal of electrons from the floating gate 54 ) is assumed to occur as a result of FN tunneling from the floating gate 54 to the P-well PW 0 , PW 1 , . . . PW n as for the split gate array.
• both the source S and split gate nonvolatile memory transistors 51 in FIG. 5 and 61 in FIG. 6 are turned off and the selected P-well PW 0 , PW 1 , . . . PW n is accumulated. Only the first byte of the row is erased (byte erase) since the P-wells PW 0 , PW 1 , . . . PW n of all the other bytes on the same row are at ground potential and the voltage between the floating gate 54 in FIG. 5 and 64 in FIG. 6 and the channel (9 V * the cell coupling ratio) is not enough for generating any significant amount of FN tunneling current.
• the cell is selectively programmed using CHE injected into the floating gate 54 in FIG. 5 and 64 in FIG. 6 using the conditions of Table 3, and the threshold is raised to a positive value safely above Vcc. This is the same mechanism used in the stacked gate cell.
• the source select transistor T 0 , T 1 , . . . T 2n , T 2n+1 which is a NMOS transistor designed to be an enhancement type, is turned on bringing the voltage of the common source of the cells of that row close to ground.
• the erased threshold can be set to a convenient negative value, since, during reading of the selected cell, the other cells connected to the selected bitline B 0,0 , B 0,1 , . . . B 0,7 , irrespective of their state, cannot contribute any current because their sources are floating.
• the high voltage requirements for the array of this embodiment are the same as for the stacked gate cell array, with one major difference.
• the memory select transistor has 16 V across its gate and for reliability reason an oxide thickness of at least 250 A has to be used.
• the source select transistor T 0 , T 1 , . . . T 2n , T 2n+1 has to be able to sustain reliably only 6 V on the junction with the gate grounded.
• the gate oxide thickness of the source S and split gate nonvolatile memory transistors 51 in FIG. 5 and 61 in FIG. 6 may be the same (250 A for the voltages used).
• the stacked gate array described before uses a much thinner gate oxide on the source select transistor T 0 , T 1 , . . . T 2n , T 2n+1 and the peripheral high voltage transistors. In this respect it is expected that a larger read current can be obtained on the stacked gate array as compared to the split cell.
• the main limitation is caused by the presence of the memory select transistors and its relatively thick gate oxide.
• the main advantage of using the cell of split gate nonvolatile memory transistors 51 in FIG. 5 and 61 in FIG. 6 is the elimination of the stacked gate patterning step in the process, since the same mask and etch used for defining the logic gates can be used to define the memory wordlines. If a lower cell read current can be tolerated, it is easier to integrate these memory arrays into logic CMOS process.
• an array of memory cells uses PMOS memory cells.
• the electrical schematic diagram of the array is the same as shown in FIG. 1 and the layout as in FIG. 2 , but the memory cells are stacked gate PMOS cell and are built on isolated N-Wells instead of P-Wells.
• the source select transistors are PMOS devices.
• Erasing increases the threshold setting the cell off during the read operation.
• the erase is the non-selective operation (all the cells of one row or of one byte are simultaneously erased).
• Programming is the selective operation (only one cell is programmed). The proposed mechanisms for programming and erasing are well known in the art.
• Erase occurs by FN tunneling of electrons from the floating gate under the selected row to the channel (channel erase).
• channel erase Under the bias conditions of Table 4 the channels of the memory gates under the selected row are inverted and at the same potential of the N-well. If byte erase is desired, the wordlines of the non-selected bytes are either at ⁇ 8 or 8 V and the non-selected wells are grounded. For these bytes the voltage available between the floating gate and the channel (8 V * the coupling ratio to the channel) is too low for FN tunneling.
• V gp indicates a voltage usually comprised between 0 and 3 V. It is tuned for maximum electron injection efficiency and is process dependent.
• the cell to be programmed is initially in a non-conductive state, it has been shown that efficient electron injection occurs if the source-drain bias is above the punch-through voltage of the cell, which is dependent on the channel length of the memory transistor.
• the cell can be programmed to a normally on state since during the read operation the non selected bitlines B 0,0 , B 0,1 , . . . B 0,7 of the selected byte are at the same potential of the source S and the sources of the non selected rows are floating (source select transistor is turned off). This is the same as for the NMOS array.
• the source select transistor has to be able to sustain reliably +/ ⁇ 8 V between the gate and the source, drain and body terminals. For the reason stated before, a gate oxide thickness of ⁇ 130 A is adequate.
• the well select CMOS transistors have to sustain +8 V between any terminals.
• enhancement type CMOS devices with ⁇ 130 A gate oxide need to be available. The high voltage requirements for this array are very low and within the capabilities of the logic source drain diffusions down to 0.18 um level of scaling.
• the process flow described herein for fabricating the NMOS cells can be used for fabricating the arrays with the PMOS cells.
• the Deep N-well step can in principle be omitted, but the designs of the peripheral circuits which use negative bias usually requires a P-well, which can go negative below ground. Using the logic N-well for isolating the P-well is quite a difficult task.
• these arrays can be fabricated using a standard Logic Process with the addition of 5 masking operations describe before.
• the same array configuration described in FIGS. 3 and 4 can be used by replacing the stacked NMOS memory cell with the PMOS cell and by switching the polarity of the wells.
• Erase occurs by FN tunneling of electrons from the floating gate under the selected row to the channel (channel erase).
• the channels of the memory gates under the selected row are inverted and at the same potential of the N-well.
• Only the sources of memory cell, source S 0 , bitline B 0,0 and wordline W 0 (cell 0,0,0) are at 8 V. It can be easily seen that the sources of all the other bytes are floating either because the source select transistors are turned off or the source lines are floating.
• the values of the voltages indicated in Table 5 are typical for this type of cell, but they may vary depending on the process technology and the geometry of the cell.
• Programming of the cell occurs as a result of hot electrons injection into the floating gate generated by impact ionization of holes moving from the source to the drain as for the stacked gate PMOS array described before.
• High voltage requirements are the same as for the stacked gate PMOS array and also the process complexity is the same.
• the electrical schematic diagram of the array is the same as shown in FIG. 5 and the layout as in FIG. 6 , but split gate PMOS cells, built on isolated N-Wells instead of P-Wells, are used.
• the source select transistors are PMOS devices.
• Erasing occurs by FN tunneling of electrons from the floating gate under the selected row to the channel.
• the values of the voltages indicated in Table 6 are typical for this type of cell, but they may vary depending on the process technology and the geometry of the cell.
• both the source S and memory select transistors under the selected row are turned on and at the same potential of the N-well.
• the bitlines B 0,0 , B 0,1 , . . . B 0,7 of the non-selected bytes are at ground potential as the wells.
• the voltage available between the floating gate 54 in FIG. 5 and 64 in FIG. 6 and the channel (8 V * the coupling ratio to the channel) is too low for EN tunneling.
• Programming of the cell occurs as a result of hot electrons injection into the floating gate 54 in FIG. 5 and 64 in FIG. 6 generated by impact ionization of holes moving from the source to the drain as for the stacked gate PMOS cell.
• the source S and memory select transistors under the selected row are turned on and the memory cell is designed to reach punch-through. It is also assumed, as it is customarily done in Flash or EEPROM arrays with PMOS memory cells, that the programming operation is always preceded by the erase operation.
• the cell can be programmed to a normally on state since during the read operation, the memory select transistor of the mirrored cell is turned off, the memory cells on the non selected bitlines B 0,0 , B 0,1 , . . . B 0,7 of the selected byte are at the same potential of the source and the sources of the non-selected rows are floating (source select transistor T 0 , T 1 , . . . T 2n , T 2n+1 is turned off).
• FIG. 7 is an electrical schematic diagram of the memory array of the OTP nonvolatile memory cell array 70 .
• the One Time Programmable (OTP) memory array 70 of FIG. 7 is made of OTP nonvolatile memory transistor 71 .
• the OTP nonvolatile memory cell array 70 circuit depicted in FIG. 7 is similar to the nonvolatile memory cell array 10 circuit depicted in FIG. 1 with the differences note below.
• Each OTP nonvolatile memory cell array 70 has a source 72 , a drain 73 , and a floating gate 74 . Note the absence of a control gate as in nonvolatile memory cell array 10 of FIG. 1 control 15 . There is no control gate because this is a One Time Programmable nonvolatile memory cell array and the control gate is not needed for erase due to UV erase.
• Wordlines W 0 , W 1 , . . . W 2n , W 2n+1 are used to select half of a given row of OTP nonvolatile memory transistors 71 of the OTP nonvolatile memory cell array 70 .
• Each of the wordlines W 0 , W 1 , . . . W 2n , W 2n+1 activates a source select transistor T 0 , T 1 , . . . T 2n , T 2n+1 .
• OTP nonvolatile memory cell array 70 with configuration described before for the PMOS cell can be used very effectively for an OTP array.
• a PMOS nonvolatile memory transistors 71 which can be fabricated in a standard CMOS process without adding new steps, have been proposed using the logic PMOS device with the gate floating 74 as the memory device and the NMOS logic transistor for accessing the memory.
• the memory cell is programmed to be normally on, erasing can only be done by UV erase.
• This array can be used for One Time Programmable (OTP) memory functions.
• Programming of a cell (0,0 for example) is done by applying for instance 6 V to the N-well and the source S. Also, grounding bitline B 0,0 and wordline W 0 with the source select transistor T 0 being turned on.
• the channel length of the cell is adjusted so that the memory cell is in punch-through under these conditions and the resultant channel current creates hot electrons which are injected into the floating gate.
• the PMOS nonvolatile memory transistors 71 use the standard PMOS device of a logic CMOS process with no additional steps added.
• This configuration can use either the split nonvolatile memory transistors or stacked gate nonvolatile memory transistors.
• FIG. 8a is a diagram of a prior art memory cell ETOX Cell 80 .
• a stacked gate nonvolatile memory transistor 83 is shown in FIG. 8 b.
• a split gate nonvolatile memory transistor 85 is shown in FIG. 8 c.
• the portion of the wordline W 0 , W 1 , . . . W 2n , W 2+1 over the diffusion area is called the memory select gate 86 .
• This memory select gate 86 is some fraction of the total floating gate 87 .
• Both nonvolatile memory transistors, stacked and split, have the same width of the ETOX cell.
• the height of the cell with separate source S is increased because of the need of separating the source S of one row from the adjacent one.
• the height of the split gate width is increased because of the need of adding the select gate.
• the increase in cell size for both the separate source or split gate cell is around 30%.
• the increase is actually less because the deep source junction used in the ETOX cell is not needed and the channel length of the stacked gate nonvolatile memory transistor cell can also be reduced because because of the reduced source to drain bias used for programming of the nonvolatile memory transistor cell.
• the currents required for programming selectively the PMOS nonvolatile memory transistor cells are an order of magnitudes lower than the programming current of the ETOX cell. This reduces the size of the charge pumps.
• the size of any of the memory arrays including peripheral circuits, which uses the PMOS or NMOS nonvolatile memory transistor cells, either stacked or split gate, is going to be very close to that of an ETOX array.

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