USRE44998E1 - Optimized thin film capacitors - Google Patents

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Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
  • H01P5/00—Coupling devices of the waveguide type
  • H01P5/04—Coupling devices of the waveguide type with variable factor of coupling
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01Q—ANTENNAS, i.e. RADIO AERIALS
  • H01Q1/00—Details of, or arrangements associated with, antennas
  • H01Q1/06—Means for the lighting or illuminating of antennas, e.g. for purpose of warning
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01Q—ANTENNAS, i.e. RADIO AERIALS
  • H01Q1/00—Details of, or arrangements associated with, antennas
  • H01Q1/12—Supports; Mounting means
  • H01Q1/1242—Rigid masts specially adapted for supporting an aerial
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01Q—ANTENNAS, i.e. RADIO AERIALS
  • H01Q1/00—Details of, or arrangements associated with, antennas
  • H01Q1/12—Supports; Mounting means
  • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
  • H01Q1/24—Supports; Mounting means by structural association with other equipment or articles with receiving set
  • H01Q1/241—Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM
  • H01Q1/242—Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM specially adapted for hand-held use
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01Q—ANTENNAS, i.e. RADIO AERIALS
  • H01Q1/00—Details of, or arrangements associated with, antennas
  • H01Q1/42—Housings not intimately mechanically associated with radiating elements, e.g. radome
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01Q—ANTENNAS, i.e. RADIO AERIALS
  • H01Q21/00—Antenna arrays or systems
  • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
  • H01Q21/061—Two dimensional planar arrays
  • H01Q21/065—Patch antenna array
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01Q—ANTENNAS, i.e. RADIO AERIALS
  • H01Q21/00—Antenna arrays or systems
  • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
  • H01Q21/20—Arrays of individually energised antenna units similarly polarised and spaced apart the units being spaced along or adjacent to a curvilinear path
  • H01Q21/205—Arrays of individually energised antenna units similarly polarised and spaced apart the units being spaced along or adjacent to a curvilinear path providing an omnidirectional coverage
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01Q—ANTENNAS, i.e. RADIO AERIALS
  • H01Q21/00—Antenna arrays or systems
  • H01Q21/28—Combinations of substantially independent non-interacting antenna units or systems
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/02—Transmitters
  • H04B1/04—Circuits
  • H04B1/0458—Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
  • H03H2001/0014—Capacitor filters, i.e. capacitors whose parasitic inductance is of relevance to consider it as filter

Definitions

• Wireless communications is a rapidly growing segment of the communications industry, with the potential to provide high-speed high-quality information exchange between portable devices located anywhere in the world.
• Potential applications enabled by this technology include multimedia internet-enabled cell phones, smart homes, appliances, automated highway systems, distance learning, and autonomous sensor networks, just to name a few. Supporting these applications using wireless techniques poses significant technical challenge. As handsets move to meet broadband, the requirements of components are more astringent. Electrical communication systems demand new more efficient low loss devices that can be used at higher frequency ranges.
• BST thin films have been used in microwave circuit applications because of their high dielectric constant, high tunability, low loss, and fast switching speed. Tunable BST films have been demonstrated as an attractive technology to low cost agile mobile circuits, such as tunable filters, tunable matching networks at a high tunable frequency range. Most of these technologies have focused on material quality, choice of electrodes, and deposition or processing techniques. As the technology matures, several issues have arisen due to the deposition methods and limited choice of electrode materials available due to the extreme deposition temperatures. Quality factor, resonance frequency and breakdown voltage are important factors for determining which applications BST thin films will work best in. High-frequency device losses consist of material-related losses in the film and at the electrode-film interface, as well as the resistive losses in the electrodes.
• At least an embodiment of the present technology provides a capacitor, comprising a substrate, a first solid electrode disposed on the substrate, a second electrode broken into subsections, the subsections connected by a bus line and separated from the first electric by a dielectric medium.
• the second electrode broken into subsections may have a lower resistance than the first solid electrode and by changing the width and length of the sides of the subsections, the resistance of the first electrode is modifiable.
• the present technology further provides a BST thinfilm design structure that by varying the Width/Length aspect ratio it optimizes electrode structure that allows for the creation of very high “Q” (low resistance) capacitors.
• the design structure relates to common capacitor material structures wherein one electrode is made from a higher resistance metal than the opposite electrode. Capacitors with such material properties can be found in planar integrated capacitors, as well as discrete ceramic capacitors.
• the inventive structure also reduces the mechanical stresses generated in the metals and dielectric films of the capacitor.
• FIG. 1 depicts a prior art structure where the BST dielectric material is sandwiched between a top and a bottom electrode.
• FIG. 2 depicts an embodiment of the prior art technology in 3D, where it contains a stack of a thinfilm deposited electrode terminals and BST materials on top of a substrate.
• FIG. 3 depicts a micro-image close-up of the top of two series capacitors as described in FIG. 2 .
• FIG. 4 depicts an embodiment of the inventive technology in 3D, where it contains a stack of a thinfilm diamond shaped deposited electrode terminals and BST materials on top of a substrate.
• FIG. 5 depicts a micro-image close-up of the top of two series capacitors as described in FIG. 4 .
• FIG. 6 depicts the top view of an embodiment of the inventive technology, said view depicts thinfilm diamond ring shaped electrode terminal with internal islands deposited terminals on top of BST materials and a substrate.
• FIG. 7 depicts the top view of an embodiment of the inventive technology, where it depicts thinfilm terminals deposited to form a zigzag space on top of BST materials and a substrate.
• FIG. 1 depicts a prior art structure where the BST dielectric material 14 is sandwiched between a top 18 and a bottom electrode 12 .
• the FIG. 1 structure shows a typical capacitor design. The structure is most appropriate when used at the low end of the radio frequency spectrum.
• This conventional integrated parallel-plate overlay capacitor structure of FIG. 2 where the bottom electrode 204 A thickness is constrained by the BST film thickness 203 .
• the losses in the thin bottom electrodes 204 A limit the overall high frequency quality factor of the BST capacitors.
• the higher electrical field between the top 201 and bottom electrodes 204 A at the edge of the cross-over 205 creates premature breakdown under the application of high bias voltages or large ac signals to the BST capacitor.
• FIG. 3 depicts a typical tuning capacitor fabricated with BST materials. These micrographs shows the dimension of a standard 0603 surface mount package and the size of active area 205 of the capacitor is just 150 micrometers square. A 0201 surface mount package would be 250 micrometers by 500 micrometers and a wire bonded package using this technology would be as small as 60 micrometers by 60 micrometers.
• a first bottom electrode such as Platinum 204 A is patterned and deposited into the substrate. At least a thinfilm coating of a BST type material 203 is then deposited on top of the first electrode 204 A. At least a second electrode 201 (which confines the active area) is deposited on top the BST film 203 .
• top electrode 201 that usually defines the capacitance of the device.
• At least one final interconnect (or bus) 204 B is deposited over the thin film structure to provide attachment to the microwave circuit and at least an electrical path to the bottom Platinum electrode 204 A.
• the top electrode 201 and the bus 204 B are made of materials comprising sputtered or deposited Gold, Aluminum and Silver.
• at least a polymer encapsulation is deposited to provide protection from the ambient and as a humidity barrier.
• a person skilled in the art may deposit multiple layers of BST thinfilm and electrodes creating an elaborate 3D structure of multiple layers capacitor stack.
• high frequency refers to the radio spectrum between 3 MHZ to 30 GHz, which includes both the “RF” spectrum and the “microwave spectrum”. It shall be further understood that a “device” comprises multiple “components” both “passive components” and “active components” and a “3D” device may comprise multiple layers stacked vertically.
• Creep is the term given to the material deformation that occurs as a result of long term exposure to levels of stress that are below the yield or ultimate strength. The rate of this damage is a function of the material properties, the exposure time, exposure temperature and the applied load (stress). Creep is usually experienced when the device is heated and cooled as a function of use or environmental temperature fluctuations. Such failures may be caused either by direct thermal loads or by electrical resistive loads, which in turn generate excessive localized thermal stresses. Depending on the magnitude of the applied stress and its duration, the deformation may become so large that it will experience brittle and/or ductile fracture, interfacial separation and creep rupture.
• An embodiment of the inventive technology may comprise at least one electrode structure that allows for the creation of very high “Q” (low resistance) capacitors.
• the technology is particularly well suited to common capacitor material structures wherein at least one electrode is made from a higher resistance metal than the opposite electrode.
• High resistance electrodes comprise and are not limited to Tungsten, Platinum, Rhodium, Chrome, Titanium/Tungsten and Nickel composites. Examples of capacitors with such material properties can be found in planar integrated capacitors, as well as discrete ceramic capacitors.
• the inventive structure further reduces the mechanical stresses, creep and other thermal generated stresses in the metals and dielectric films of the capacitor.
• the broken electrode usually carries the lower resistance of the two.
• the broken electrode distributes the signal across the capacitor area and, through proper arrangement, increases the effective width of the signal path through the higher resistance solid electrode.
• the signal busses (electrical metal connections) bring in and take out the signal.
• the inventive technology comprises at least a broken electrode and bussing where the broken electrode can be used in all kinds of capacitors, and may find applicability in transistor structures.
• the inventive structure realizes these benefits by breaking at least two of the electrodes of a pair of series capacitors into subsections.
• W Width
• L Length
• the sections are arranged in such that it increases the effective Width 207 of the signal path in the higher resistance electrode 204 A.
• These subsections are then electrically connected through a bus 501 as seen in the micrograph of FIG. 5 .
• 207 has to be maximized in order to increase the active area 205 .
• the length (L) 206 dimension will usually be fixed because of lithographic constraints, therefore by modifying the (W) 207 dimension and duplicating the structure as seen in FIG. 4 , the active area is significantly increased and the change in capacitance can be as high as 5 to 1.
• An embodiment of the present technology allows for the creation of a wide frequency of tuning, and some of the preferred applications include but are not limited to low loss phase shifters for high electronically scanning antennas.
• FIG. 4 depicts one embodiment of the invention in which the reduction of the original breaking of the electrode increases the width to 4.25 times that of the conventional capacitor of FIG. 2 and FIG. 3 .
• the bus 501 is not shown in FIG. 4 for clarity purposes.
• FIG. 4 depicts at least one preferred method of manufacture the inventive capacitor 3D stack.
• It comprises the steps of forming a multilayer BST composite by sputter blanket PARASCAN from Paratek Inc. (35 target) on top of a Gennum Inc. 0.2 um Pt substrate.
• a Gold (Au) top electrode is patterned using conventional semiconductor lithographic techniques and sputtered on top in order to create the interconnections between the top and bottom electrodes.
• the embodiment may also include at least one buffer layer. The wafer will be diced into approximate 4 of 1 ⁇ 2 by 1 ⁇ 2 after the PARASCAN deposition.
• FIG. 6 and FIG. 7 depict capacitors without the interconnection bus 501 for clarity.
• the bus 501 may be patterned and deposited by one skilled in the art in order to create parallel or series capacitors.
• Two embodiments of technology are shown FIG. 6 and FIG. 7 . These embodiments include and at least a solid bottom electrode, the electrodes broken into subsections FIG.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
• Semiconductor Integrated Circuits (AREA)

Abstract

Description

Claims (20)

Priority Applications (1)

Applications Claiming Priority (3)

Related Parent Applications (1)

Publications (1)

Family

ID=43733198

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Families Citing this family (7)

Citations (224)

• 2006
  • 2006-11-20 US US11/602,114 patent/US8064188B2/en not_active Ceased
• 2012
  • 2012-03-09 US US13/416,810 patent/USRE44998E1/en not_active Expired - Fee Related

Patent Citations (261)

Non-Patent Citations (29)

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