WO2021036610A1 - Digital-to-analog converter of r-2r ladder-shaped network architecture - Google Patents
- ️Thu Mar 04 2021
本发明涉及电路设计技术领域，更具体地，涉及一种R-2R梯形网络架构的数模转换器。The present invention relates to the technical field of circuit design, and more specifically, to a digital-to-analog converter with an R-2R ladder network architecture.
背景技术Background technique在今日的通讯、计算机系统、电子产品及高画质电视的应用中，高速数字模拟转换器(Digital to Analog converter，DAC)有着非常重要的功能及地位，它的功能是将数字编码精准地转换为模拟讯号，其性能往往决定了终端商品的优劣。In today’s communications, computer systems, electronic products and high-definition television applications, the high-speed digital-to-analog converter (DAC) has a very important function and position. Its function is to accurately convert digital codes. For the analog signal, its performance often determines the pros and cons of the terminal product.
DAC有很多不同种类的架构，其中R-2R阶梯网络架构的数字模拟转换器是很常见且简单的一种架构。但是，传统R-2R阶梯网络架构的数字模拟转换器存在一个很大的缺点，就是开关的导通阻抗要随着位数的增加而减少，每增加一位需减少原本一半阻抗，以维持R-2R阶梯网络架构的电阻比例。而在集成电路的制作上，开关通常使用NMOS管来制作，而如果使得开关的导通阻抗减半，就必须将并联的NMOS管的数量加倍。DAC has many different types of architectures. Among them, the R-2R ladder network architecture digital-to-analog converter is a very common and simple architecture. However, the traditional R-2R ladder network architecture digital-to-analog converter has a big disadvantage, that is, the on-resistance of the switch decreases with the increase of the number of bits. Each additional bit needs to reduce the original impedance by half to maintain R The resistance ratio of -2R ladder network architecture. In the production of integrated circuits, switches are usually made of NMOS transistors, and if the on-resistance of the switch is halved, the number of parallel NMOS transistors must be doubled.
图1a为现有的9位的R-2R阶梯网络架构的数模转换器的电路示意图，图1b为图1a中数模转换器的等效电路示意图，图1a中的M表示对应位并联的NMOS管的数量。图1a和图1b中所标识的R和2R为对应电阻的阻抗，b0～b8分别为9位数字信号的输入位，r为每个NMOS管的导通阻抗，VIN为数模转换器的电源端，VDD为数模转换器的参考电压输入端，IOUT为数模转换器的电流输出端。Figure 1a is a schematic circuit diagram of the existing 9-bit R-2R ladder network architecture digital-to-analog converter, Figure 1b is a schematic diagram of the equivalent circuit of the digital-to-analog converter in Figure 1a, and M in Figure 1a represents the parallel connection of the corresponding bits The number of NMOS tubes. R and 2R marked in Figure 1a and Figure 1b are the impedances of the corresponding resistors, b0～b8 are the input bits of 9-bit digital signals, r is the on-resistance of each NMOS tube, and VIN is the power supply of the digital-to-analog converter. VDD is the reference voltage input terminal of the digital-to-analog converter, and IOUT is the current output terminal of the digital-to-analog converter.
根据图1a和图1b可以看出，在9位的R-2R阶梯网络架构的数模转换器中总共需要256颗NMOS管，来维持R-2R阶梯网络架构的电阻比例。According to Figure 1a and Figure 1b, it can be seen that a total of 256 NMOS transistors are required in the 9-bit R-2R ladder network architecture digital-to-analog converter to maintain the resistance ratio of the R-2R ladder network architecture.
如果数字模拟转换器中的NMOS的数量太多，不仅会使得电路面积变大，还会导致其寄生电容非常大，对于开关切换时的瞬时响应会有非常 大的RC时间常数，导致整个电路的操作速度将严重降低，并且会有大的噪声(glitch)产生，影响电路的动态效能。此外，随着R-2R阶梯网络架构位数的增加，NMOS管的数量也必须一直以2的次方倍增，使每位的NMOS管的开关匹配越来越难实现，让制程偏移造成的不匹配的问题越来越严重，使得DNL(Differential Nonlinearity，差分非线性)变差。If the number of NMOS in the digital-to-analog converter is too large, it will not only increase the circuit area, but also cause its parasitic capacitance to be very large. There will be a very large RC time constant for the transient response of the switch, which will cause the entire circuit The operating speed will be severely reduced, and large noise (glitch) will be generated, which will affect the dynamic performance of the circuit. In addition, as the number of bits in the R-2R ladder network architecture increases, the number of NMOS transistors must always be multiplied by the power of 2, making it more and more difficult to achieve the switch matching of each NMOS transistor, which is caused by process shifts. The problem of mismatch is getting more and more serious, making DNL (Differential Nonlinearity, differential nonlinearity) worse.
发明内容Summary of the invention
本发明实施例的一个目的是提供一种R-2R梯形网络架构的数模转换器的新的技术方案。An object of the embodiments of the present invention is to provide a new technical solution for the digital-to-analog converter of the R-2R ladder network architecture.
根据本发明的第一方面，提供了一种R-2R梯形网络架构的数模转换器，所述数模转换器为由串联的第一开关和第一电阻、与串联的第二开关和第二电阻组成的R-2R梯形网络结构，所述数模转换器的每一位串联的第一开关的导通阻抗与第一电阻的阻抗之和，为第二开关的导通阻抗与第二电阻的阻抗之和的一半，以使经过每一位支路的电流为经过相邻的高一位支路的电流的一半。According to the first aspect of the present invention, there is provided a digital-to-analog converter with an R-2R ladder network architecture. The digital-to-analog converter consists of a first switch and a first resistor connected in series, and a second switch and a The R-2R ladder network structure composed of two resistors. The sum of the on-resistance of the first switch and the impedance of the first resistor of each bit of the digital-to-analog converter is the on-resistance of the second switch and the second The resistance is half of the sum of the impedances, so that the current passing through each branch is half of the current passing through the adjacent higher branch.
可选的，所述R-2R梯形网络结构中，每一位的第二开关和第二电阻的串联支路与相邻的低一位的支路并联。Optionally, in the R-2R ladder network structure, the series branch of the second switch and the second resistor of each bit is connected in parallel with the adjacent lower bit branch.
可选的，所述第一电阻的阻抗是所述第二电阻的阻抗的一半，且所述第一开关的导通阻抗为所述第二开关的导通阻抗的一半。Optionally, the impedance of the first resistor is half of the impedance of the second resistor, and the on-resistance of the first switch is half of the on-resistance of the second switch.
可选的，所述R-2R梯形网络结构中还包括由第三开关和第三电阻组成的串联支路，所述串联支路与最低位的第二开关和第二电阻并联连接，其中，所述第三开关的导通阻抗和所述第三电阻的阻抗之和，与最低位的第二开关的导通阻抗和第二电阻的阻抗之和相等。Optionally, the R-2R ladder network structure further includes a series branch composed of a third switch and a third resistor, and the series branch is connected in parallel with the lowest second switch and the second resistor, wherein, The sum of the on-resistance of the third switch and the impedance of the third resistor is equal to the sum of the on-resistance of the lowest second switch and the impedance of the second resistor.
可选的，所述第三电阻的阻抗和最低位的第二电阻的阻抗相等，所述第三开关的阻抗和最低位的第二开关的阻抗相等。Optionally, the impedance of the third resistor is equal to the impedance of the second lowest resistance, and the impedance of the third switch is equal to the impedance of the second lowest switch.
可选的，所述第一开关的控制端、及所述第三开关的控制端均与所述数模转换器的基准电压输入端连接。Optionally, the control terminal of the first switch and the control terminal of the third switch are both connected to the reference voltage input terminal of the digital-to-analog converter.
可选的，每一位的第二开关均包括相同数量个并联连接的NMOS管。Optionally, the second switch of each position includes the same number of NMOS transistors connected in parallel.
可选的，每一位的第二开关中，并联连接的NMOS管的数量为2。Optionally, in each second switch, the number of NMOS transistors connected in parallel is two.
可选的，每一位的第一开关包括对应数量个并联连接的NMOS管。Optionally, the first switch of each position includes a corresponding number of NMOS transistors connected in parallel.
可选的，所述数模转换器为9位，低5位的第一开关均包括4个并联连接的NMOS管；第6位的第一开关包括6个并联连接的NMOS管；第7位的第一开关包括8个并联连接的NMOS管；第8位的第一开关包括12个并联连接的NMOS管。Optionally, the digital-to-analog converter has 9 bits, the first switch of the lower 5 bits includes 4 NMOS transistors connected in parallel; the first switch of the 6th position includes 6 NMOS transistors connected in parallel; the 7th position The first switch includes 8 NMOS transistors connected in parallel; the first switch of the 8th position includes 12 NMOS transistors connected in parallel.
本发明的一个有益效果在于，在本发明的实施例中，使得每一位串联的第一开关的导通阻抗与第一电阻的阻抗之和，为第二开关的导通阻抗与第二电阻的阻抗之和的一半，以使经过每一位支路的电流为经过相邻的高一位支路的电流的一半，可以保证R-2R梯形网络架构的规则不被破坏，而且，可以在数模转换器的位数过多时，减小电路面积。One beneficial effect of the present invention is that, in the embodiments of the present invention, the sum of the on-resistance and the on-resistance of each first switch connected in series is the on-resistance and the on-resistance of the second switch. So that the current passing through each branch is half of the current passing through the adjacent higher branch, which can ensure that the rules of the R-2R ladder network architecture are not destroyed, and can be used in When the number of digits of the digital-to-analog converter is too large, reduce the circuit area.
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。Through the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, other features and advantages of the present invention will become clear.
附图说明Description of the drawings被结合在说明书中并构成说明书的一部分的附图示出了本发明的实施例，并且连同其说明一起用于解释本发明的原理。The drawings incorporated in the specification and constituting a part of the specification illustrate the embodiments of the present invention, and together with the description are used to explain the principle of the present invention.
图1a为现有的9位的R-2R阶梯网络架构的数模转换器的电路示意图；Figure 1a is a circuit diagram of a conventional 9-bit R-2R ladder network architecture digital-to-analog converter;
图1b为图1a中数模转换器的等效电路示意图；Fig. 1b is a schematic diagram of an equivalent circuit of the digital-to-analog converter in Fig. 1a;
图2为根据本发明实施例的R-2R梯形网络架构的数模转换器的电路示意图；2 is a schematic circuit diagram of a digital-to-analog converter of an R-2R ladder network architecture according to an embodiment of the present invention;
图3为根据本发明实施例的9位R-2R梯形网络架构的数模转换器的电路示意图；3 is a schematic circuit diagram of a digital-to-analog converter with a 9-bit R-2R ladder network architecture according to an embodiment of the present invention;
图4为图3中数模转换器的等效电路示意图；Fig. 4 is a schematic diagram of an equivalent circuit of the digital-to-analog converter in Fig. 3;
图5为图1a中的数模转换器中电流输出的模拟波形图；Fig. 5 is an analog waveform diagram of the current output in the digital-to-analog converter in Fig. 1a;
图6为图3中的数模转换器中电流输出的模拟波形图；Fig. 6 is an analog waveform diagram of the current output in the digital-to-analog converter in Fig. 3;
图7为图1a中的数模转换器的DNL计算结果示意图；Fig. 7 is a schematic diagram of the DNL calculation result of the digital-to-analog converter in Fig. 1a;
图8为图3中的数模转换器的DNL计算结果示意图。FIG. 8 is a schematic diagram of the DNL calculation result of the digital-to-analog converter in FIG. 3.
具体实施方式detailed description现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that unless specifically stated otherwise, the relative arrangement of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention.
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。The following description of at least one exemplary embodiment is actually only illustrative, and in no way serves as any limitation to the present invention and its application or use.
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。The technologies, methods, and equipment known to those of ordinary skill in the relevant fields may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be regarded as part of the specification.
在这里示出和讨论的所有例子中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它例子可以具有不同的值。In all examples shown and discussed herein, any specific value should be interpreted as merely exemplary, rather than as a limitation. Therefore, other examples of the exemplary embodiment may have different values.
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。It should be noted that similar reference numerals and letters indicate similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
图2为本发明一个实施例的R-2R梯形网络架构的数模转换器的电路原理图。Fig. 2 is a schematic circuit diagram of a digital-to-analog converter of an R-2R ladder network architecture according to an embodiment of the present invention.
根据图2所示，该R-2R梯形网络架构的数模转换器可以是N位，其中，N为任意正整数。According to Figure 2, the digital-to-analog converter of the R-2R ladder network architecture can be N bits, where N is any positive integer.
该数模转换器为由串联的第一开关S1 i和第一电阻R1 i、与串联的第二开关S2 i和第二电阻R2 i组成的R-2R梯形网络结构，其中，i∈[1，N]。 The digital-to-analog converter is an R-2R ladder network structure composed of a first switch S1 i and a first resistor R1 i connected in series, and a second switch S2 i and a second resistor R2 i connected in series, where i∈[1 , N].
在该R-2R梯形网络架构的数模转换器中，每一位串联的第一开关S1 i的导通阻抗与第一电阻R1 i的阻抗之和，为第二开关S2 i的导通阻抗与第二电阻R2 i的阻抗之和的一半，以使经过每一位支路的电流为经过相邻的高一位支路的电流的一半。 In the digital-to-analog converter of the R-2R ladder network architecture, the sum of the on-resistance of each first switch S1 i connected in series and the impedance of the first resistor R1 i is the on-resistance of the second switch S2 i And half of the sum of the impedance of the second resistor R2 i , so that the current passing through each branch is half of the current passing through the adjacent higher branch.
在一个实施例中，对于R-2R梯形网络架构的数模转换器的第i(i∈[1，N])位，第一开关S1 i的导通阻抗的阻抗为r11，第一电阻R1 i的阻抗为r12，第二开关S2 i的导通阻抗为r21，第二电阻R2 i的阻抗为r22，那么，第一开关S1 i的导通阻抗与第一电阻R1 i的阻抗之和为r11+r12，为第二开关 S2 i的导通阻抗与第二电阻R2 i的阻抗之和为r21+r22，且2*(r11+r12)＝r21+r22。 In one embodiment, for the i-th (i∈[1,N]) bit of the digital-to-analog converter of the R-2R ladder network architecture, the impedance of the on-resistance of the first switch S1 i is r11, and the first resistance R1 The impedance of i is r12, the on-resistance of the second switch S2 i is r21, and the impedance of the second resistor R2 i is r22. Then, the sum of the on-resistance of the first switch S1 i and the impedance of the first resistor R1 i is r11+r12, the sum of the on-resistance of the second switch S2 i and the impedance of the second resistor R2 i is r21+r22, and 2*(r11+r12)=r21+r22.
例如，对于第3位，第一开关S1 3的导通阻抗的阻抗与第一电阻R1 3的阻抗之和r11+r12，为第二开关S2 3的导通阻抗与第二电阻R2 3的阻抗之和r21+r22的一半。 For example, for the third position, the sum of the impedance of the on-resistance of the first switch S1 3 and the impedance of the first resistor R1 3 is r11+r12, which is the on-resistance of the second switch S2 3 and the impedance of the second resistor R2 3 The sum is half of r21+r22.
在本实施例中，经过第i位支路的电流I i具体为经过第i位的第一开关S1 i和第一电阻R1 i的电流，经过与第i位相邻的高一位支路的电流，即经过第i+1位支路的电流I i+1，具体为经过第i+1位第一开关S1 i+1和第一电阻R1 i+1的电流，其中，2*I i＝I i+1。 In this embodiment, the current I i passing through the i-th branch is specifically the current passing through the i-th first switch S1 i and the first resistor R1 i , passing through the higher-order branch adjacent to the i-th bit , That is, the current I i+1 through the i+1-th branch, specifically the current through the i+1- th first switch S1 i+1 and the first resistor R1 i+1 , where 2*I i =I i+1 .
在本实施例中，经过第i位支路中第二开关S2 i和第二电阻R2 i的电流，与经过第i-1位支路中第一开关S1 i-1和第一电阻R1 i-1的电流相等。 In this embodiment, the current passing through the second switch S2 i and the second resistor R2 i in the i-th branch is the same as the current passing through the first switch S1 i-1 and the first resistor R1 i in the i-1th branch. The currents of -1 are equal.
最高位的支路，即第N位支路中，仅包含第二开关S2 N和第二电阻R2 N，因此，需调整第二开关S2 N和第二电阻R2 N的阻抗，使得经过第N位支路中第二开关S2 N和第二电阻R2 N的电流，与经过第N-1位支路中第一开关S1 N-1和第一电阻R1 N-1的电流相等。 The highest branch, that is, the Nth branch, contains only the second switch S2 N and the second resistor R2 N. Therefore, the impedance of the second switch S2 N and the second resistor R2 N needs to be adjusted so that the The currents of the second switch S2 N and the second resistor R2 N in the bit branch are equal to the currents passing through the first switch S1 N-1 and the first resistor R1 N-1 in the N-1th bit branch.
在一个实施例中，第一开关和第二开关均可以是由单个或多个并联连接的NMOS管提供。In an embodiment, both the first switch and the second switch may be provided by a single or multiple NMOS transistors connected in parallel.
那么，在本发明的实施例中，使得每一位串联的第一开关的导通阻抗与第一电阻的阻抗之和，为第二开关的导通阻抗与第二电阻的阻抗之和的一半，以使经过每一位支路的电流为经过相邻的高一位支路的电流的一半，可以保证R-2R梯形网络架构的规则不被破坏，而且，可以在数模转换器的位数过多时，减小电路面积。此外，本发明至少一个实施例中的数模转换器还可以降低噪声，保证每一位的NMOS管的开关匹配更为容易。此外，由于电路中NMOS管的数量较少，可以减少其寄生电容，提高数模转换器的操作速度。Then, in the embodiment of the present invention, the sum of the on-resistance of each first switch connected in series and the impedance of the first resistor is half of the sum of the on-resistance of the second switch and the impedance of the second resistor. , So that the current passing through each branch is half of the current passing through the adjacent higher branch, which can ensure that the rules of the R-2R ladder network architecture are not destroyed, and can be used in the digital-to-analog converter. When the number is too large, reduce the circuit area. In addition, the digital-to-analog converter in at least one embodiment of the present invention can also reduce noise and ensure that the switch matching of each bit of the NMOS tube is easier. In addition, since the number of NMOS tubes in the circuit is small, its parasitic capacitance can be reduced, and the operating speed of the digital-to-analog converter can be improved.
另外，由于每个开关(包括第一开关、第二开关和第三开关)中所包含的NMOS管数量较少，可以获得比较好的匹配，所以，本实施例的R-2R梯形网络架构的数模转换器的DNL(Differential Nonlinearity,差分非线性)也可以得到改善，进而能提供更好的分辨率。In addition, since each switch (including the first switch, the second switch and the third switch) contains a small number of NMOS transistors, a better match can be obtained. Therefore, the R-2R ladder network architecture of this embodiment is The DNL (Differential Nonlinearity) of the digital-to-analog converter can also be improved to provide better resolution.
在一个实施例中，R-2R梯形网络结构中，每一位的第二开关和第二电阻的串联支路与相邻的低一位的支路并联。In one embodiment, in the R-2R ladder network structure, the series branch of the second switch and the second resistor of each bit is connected in parallel with the adjacent lower bit branch.
在本实施例中，第i位支路包括第一开关S1 i、第一电阻R1 i、第二开关S2 i和第二电阻R2 i，与第i位相邻的低一位的支路即为第i-1位支路，包括第一开关S1 i-1、第一电阻R1 i-1、第二开关S2 i-1和第二电阻R2 i-1，第i位支路中串联连接的第二开关S2 i和第二电阻R2 i，与第i-1位支路中的第一开关S1 i-1、第一电阻R1 i-1、第二开关S2 i-1和第二电阻R2 i-1并联连接，具体可以如图2所示。 In this embodiment, the i-th branch includes a first switch S1 i , a first resistor R1 i , a second switch S2 i, and a second resistor R2 i , and the branch of the lower one adjacent to the i-th bit is Is the i-1th branch, including a first switch S1 i-1 , a first resistor R1 i-1 , a second switch S2 i-1 and a second resistor R2 i-1 , and the i-th branch is connected in series The second switch S2 i and the second resistor R2 i , and the first switch S1 i-1 , the first resistor R1 i-1 , the second switch S2 i-1 and the second resistor in the branch i-1 R2 i-1 are connected in parallel, as shown in Figure 2.
在一个实施例中，对于每一位，第一电阻的阻抗是第二电阻的阻抗的一半，第一开关的导通阻抗是第二开关的导通阻抗的一半。In one embodiment, for each bit, the impedance of the first resistor is half of the impedance of the second resistor, and the on-resistance of the first switch is half of the on-resistance of the second switch.
例如，对于R-2R梯形网络架构的数模转换器的第i(i∈[1，N])位，第一开关S1 i的导通阻抗的阻抗为r11，第一电阻R1 i的阻抗为r12，第二开关S2 i的导通阻抗为r21，第二电阻R2 i的阻抗为r22，那么，2*r11＝r21，2*r12＝r22。 For example, for the i-th (i∈[1,N]) bit of the digital-to-analog converter of the R-2R ladder network architecture, the impedance of the on-resistance of the first switch S1 i is r11, and the impedance of the first resistor R1 i is r12, the on-resistance of the second switch S2 i is r21, and the impedance of the second resistor R2 i is r22, then 2*r11=r21, 2*r12=r22.
在一个实施例中，R-2R梯形网络架构的数模转换器中每一位的第一开关S1 i的导通阻抗的阻抗相等，第一电阻R1 i的阻抗相等，第二开关S2 i的导通阻抗相等，第二电阻R2 i的阻抗也相等。 In one embodiment, in the digital-to-analog converter of the R-2R ladder network architecture, the impedance of the on-resistance of the first switch S1 i of each bit is equal, the impedance of the first resistor R1 i is equal, and the impedance of the second switch S2 i The on-resistance is equal, and the impedance of the second resistor R2 i is also equal.
在一个实施例中，如图2所示，R-2R梯形网络结构中还包括由第三开关S3和第三电阻R3组成的串联支路，该串联支路与最低位(即第1位)的第二开关S2 1和第二电阻R2 1并联连接。其中，第三开关S3的导通阻抗r31与第三电阻R3的阻抗r32之和，与第1位的第二开关S2 1的导通阻抗r21和第二电阻R2 1的阻抗r22之和相等，即r31+r32＝r21+r22。 In one embodiment, as shown in FIG. 2, the R-2R ladder network structure further includes a series branch composed of a third switch S3 and a third resistor R3, and the series branch is connected to the lowest position (ie, the first position). a second switch S2 and a resistor R2 is connected in parallel with the second. Wherein the impedance of the third switch S3 r32 on-resistance r31 and the third resistor R3, a first and a second switch on-resistance S2 1 r21 r22 impedance and the second resistor R2 1 is equal to the sum, That is, r31+r32=r21+r22.
在本实施例中，在每一位的第一开关S1 i的导通阻抗的阻抗相等，第一电阻R1 i的阻抗相等，第二开关S2 i的导通阻抗相等，第二电阻R2 i的阻抗也相等的情况下，通过与第1位第二开关S2 1和第二电阻R2 1并联连接的第三开关S3和第三电阻R3，来使得经过第1位支路的电流I 1为经过第2位支路的电流I 2的一半，以保证R-2R梯形网络结构的规则不被破坏。 In this embodiment, the impedance of the on-resistance of the first switch S1 i in each bit is equal, the impedance of the first resistor R1 i is equal, the on-resistance of the second switch S2 i is equal, and the impedance of the second resistor R2 i is equal. impedance equal to the case, by the first bit of the second switch S2 and a third switch S3 connected in parallel to the second resistor R2 and a third resistor R3, to the first branch such that after the bit current I 1 is elapsed Half of the current I 2 of the second branch to ensure that the rules of the R-2R ladder network structure are not destroyed.
在一个实施例中，第三开关S3的导通阻抗r31与第1位的第二开关S2 1 的导通阻抗r21相等，即r31＝r21。第三电阻R3的阻抗r32与第1位的第二电阻R2 1的阻抗r22相等，即r32＝r22。 In one embodiment, the third switch S3 is turned on and the impedance of a r31 second switch on-resistance r21 is equal to S2 1, i.e., r31 = r21. R32 impedance of the third resistor R3 and the first impedance of a second resistor r22 is equal R2 1, i.e., r32 = r22.
在一个实施例中，R-2R梯形网络架构的数模转换器中每一位的第一开关的控制端、及第三开关S3的控制端均与数模转换器的基准电压输入端VDD连接。In one embodiment, the control terminal of the first switch and the control terminal of the third switch S3 of each bit of the digital-to-analog converter of the R-2R ladder network architecture are connected to the reference voltage input terminal VDD of the digital-to-analog converter .
该基准电压输入端可以为第一开关和第三开关提供用于控制其导通的控制电压，使得数模转换器在正常工作的情况下，所有的第一开关和第三开关均导通。The reference voltage input terminal can provide a control voltage for controlling the conduction of the first switch and the third switch, so that when the digital-to-analog converter works normally, all the first switch and the third switch are turned on.
在一个实施例中，R-2R梯形网络架构的数模转换器中每一位的第二开关均包括相同数量个并联连接的NMOS管。In one embodiment, each second switch in the digital-to-analog converter of the R-2R ladder network architecture includes the same number of NMOS transistors connected in parallel.
在一个实施例中，每一位的第二开关中，并联连接的NMOS管的数量可以但不限于为2。In one embodiment, in each second switch, the number of NMOS transistors connected in parallel may be but not limited to two.
在一个实施例中，每一位的第一开关包括对应数量个并联连接的NMOS管。In one embodiment, the first switch of each bit includes a corresponding number of NMOS transistors connected in parallel.
在本实施例中，不同位的第一开关所包含的NMOS管的数量可以相等，也可以不等。In this embodiment, the number of NMOS transistors included in the first switches of different positions may be equal or different.
例如，数模转换器为9位，其结构可以是如图3所示。该9位的数模转换器中，每一位的第二开关包括2个并联连接的NMOS管，第三开关S3包括2个并联连接的NMOS管，每个第二开关和第三开关的控制端均与基准电压输入端VDD连接。每一位的第二电阻的阻抗和第三电阻的阻抗相等，均为r22，每一位的第一电阻的阻抗为r11＝1/2*r22。For example, the digital-to-analog converter is 9 bits, and its structure can be as shown in Figure 3. In the 9-bit digital-to-analog converter, the second switch of each bit includes two NMOS transistors connected in parallel, and the third switch S3 includes two NMOS transistors connected in parallel. Each second switch and the third switch control Both terminals are connected to the reference voltage input terminal VDD. The impedance of the second resistor of each bit is equal to the impedance of the third resistor, which is r22, and the impedance of the first resistor of each bit is r11=1/2*r22.
低5位的第一开关均包括4个并联连接的NMOS管；第6位的第一开关包括6个并联连接的NMOS管；第7位的第一开关包括8个并联连接的NMOS管；第8位的第一开关包括12个并联连接的NMOS管。The first switch of the lower 5 positions includes 4 NMOS transistors connected in parallel; the first switch of the 6th position includes 6 NMOS transistors connected in parallel; the first switch of the 7th position includes 8 NMOS transistors connected in parallel; The 8-bit first switch includes 12 NMOS transistors connected in parallel.
在本实施例中，低5位的第一开关中所包含的每个NMOS管与第二开关中所包含的每个NMOS管的导通阻抗相等。In this embodiment, the on-resistance of each NMOS transistor included in the first switch with the lower 5 bits is equal to that of each NMOS transistor included in the second switch.
在如图3所示的数模转换器中，由于第8位支路和第9位支路均连接在数模转换器的电源端VIN连接，使得第6位支路、第7位支路、第8位支路越来越靠近输入电源端VIN，因此，NMOS管的本体效应越来越严重， 最严重的是第8位支路的第一开关中的NMOS管，其次是第7位支路的第一开关中的NMOS管，再其次是第6位支路的第一开关中的NMOS管。本体效应会影响NMOS管的等效阻抗值，本体效应越严重者其等效阻抗会比较大。因此第8位支路的第一开关中可以为12颗并联连接的NMOS管、第7位支路的第一开关中可以为8颗并联连接的NMOS管、第6位支路的第一开关中可以为6颗并联连接的NMOS管，才能均使第一开关的导通阻抗为r11。而低5位支路的第一开关中NMOS管的本体效应的影响很小，可以忽略不计，因此，低5位支路的第一开关中可以均包含4个并联连接的NMOS管。In the digital-to-analog converter shown in Figure 3, since the 8th branch and the 9th branch are both connected to the power terminal VIN of the digital-to-analog converter, the 6th branch and the 7th branch are The 8th branch is getting closer and closer to the input power terminal VIN. Therefore, the body effect of the NMOS tube is getting more and more serious. The most serious is the NMOS tube in the first switch of the 8th branch, followed by the 7th. The NMOS transistor in the first switch of the branch is followed by the NMOS transistor in the first switch of the sixth branch. The body effect will affect the equivalent impedance value of the NMOS tube. The more serious the body effect, the larger the equivalent impedance will be. Therefore, the first switch of the 8th branch can be 12 NMOS transistors connected in parallel, and the first switch of the 7th branch can be 8 NMOS transistors connected in parallel and the first switch of the 6th branch. There can be six NMOS transistors connected in parallel to make the on-resistance of the first switch r11. The influence of the body effect of the NMOS transistor in the first switch of the lower 5-bit branch is very small and can be ignored. Therefore, the first switch of the lower 5-bit branch may all include 4 NMOS transistors connected in parallel.
图4为图3中数模转换器的等效电路图。如图4所示，在该9位的数模转换器中，每一位的第一开关的导通阻抗为r11，第二开关的导通阻抗为r21，第三开关的导通阻抗为r21。Figure 4 is an equivalent circuit diagram of the digital-to-analog converter in Figure 3. As shown in Figure 4, in the 9-bit digital-to-analog converter, the on-resistance of the first switch of each bit is r11, the on-resistance of the second switch is r21, and the on-resistance of the third switch is r21 .
图5为图1a中的数模转换器中电流输出的模拟波形图，从图中可以看出，数模转换器在255bit与256bit的切换过程发生最差的噪声(glitch)状况，原因是从011111111切换到100000000之过程涉及最多NMOS管同时动作。Figure 5 is the analog waveform diagram of the current output in the digital-to-analog converter in Figure 1a. It can be seen from the figure that the worst noise (glitch) condition occurs in the digital-to-analog converter during the switching process between 255bit and 256bit. The reason is The process of switching from 011111111 to 100000000 involves at most NMOS transistors operating at the same time.
图6为图3中的数模转换器中电流输出的模拟波形图，从图中可以看出，噪声(glitch)问题可以得到明显改善。Fig. 6 is an analog waveform diagram of the current output in the digital-to-analog converter in Fig. 3. As can be seen from the figure, the glitch problem can be significantly improved.
综上，在本发明的至少一个实施例中，该数模转换器可以降低噪声振幅及持续时间。In summary, in at least one embodiment of the present invention, the digital-to-analog converter can reduce noise amplitude and duration.
图7为图1a中的数模转换器的DNL计算结果示意图，从图中可以看出，数模转换器在255bit与256bit的切换过程发生最差的DNL＝0.1LSB。Fig. 7 is a schematic diagram of the DNL calculation result of the digital-to-analog converter in Fig. 1a. It can be seen from the figure that the worst DNL=0.1LSB occurs during the switching process of the digital-to-analog converter between 255bit and 256bit.
图8为图3中的数模转换器的DNL计算结果示意图，从图中可以看出，最差的DNL也可以获得改善至0.08LSB。Fig. 8 is a schematic diagram of the DNL calculation result of the digital-to-analog converter in Fig. 3. As can be seen from the figure, the worst DNL can also be improved to 0.08LSB.
综上，在本发明的至少一个实施例中，由于每个开关(包括第一开关、第二开关和第三开关)中所包含的NMOS管数量较少，可以获得比较好的匹配，所以，本实施例的R-2R梯形网络架构的数模转换器的DNL(Differential Nonlinearity,差分非线性)也可以得到改善，进而能提供更好的分辨率。In summary, in at least one embodiment of the present invention, since the number of NMOS transistors included in each switch (including the first switch, the second switch, and the third switch) is small, better matching can be obtained. Therefore, The DNL (Differential Nonlinearity) of the digital-to-analog converter of the R-2R ladder network architecture of this embodiment can also be improved, thereby providing better resolution.
以上已经描述了本发明的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。本发明的范围由所附权利要求来限定。The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Without departing from the scope and spirit of the described embodiments, many modifications and changes are obvious to those of ordinary skill in the art. The choice of terms used herein is intended to best explain the principles, practical applications, or technical improvements in the market of the various embodiments, or to enable other ordinary skilled in the art to understand the various embodiments disclosed herein. The scope of the invention is defined by the appended claims.