WO2023004710A1 - Semiconductor device and manufacturing method therefor - Google Patents

Disclosed in embodiments of the present application are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a through-silicon via as well as a first chip, a second chip, and a fifth insulating layer stacked in sequence. The first chip comprises a first insulating layer having a first opening, and the first opening exposes a first electrical connection layer. The through-silicon via comprises a first through-silicon via section and a second through-silicon via section that are connected to each other; the first through-silicon via section is located in the first opening, and the first electrical connection layer is at the bottom of the first through-silicon via section; the second through-silicon via section runs through the second chip, and the second through-silicon via section has a bottom connected to the first through-silicon via section and a top connected to a third electrical connection layer; a first metal via has a bottom connected to a second electrical connection layer and a top connected to the third electrical connection layer; and the first electrical connection layer and the second electrical connection layer are electrically connected by means of the through-silicon via, the first metal via, and the third electrical connection layer. The implementation of the embodiments of the present application can reduce or prevent lateral etching of silicon caused by charge accumulation during a through-silicon via etching process.

一种半导体装置以及半导体装置的制作方法A kind of semiconductor device and the manufacturing method of semiconductor device 技术领域technical field

本申请涉及半导体技术领域，尤其涉及一种半导体装置以及半导体装置的制作方法。The present application relates to the technical field of semiconductors, and in particular to a semiconductor device and a manufacturing method of the semiconductor device.

背景技术Background technique

硅通孔(through silicon via，TSV)也称做硅穿孔，是一种穿透硅晶圆或芯片的垂直互连。TSV可用于实现3D集成电路封装，例如TSV可堆叠多片芯片，实现芯片或电路互联。目前，在刻蚀硅通孔的传统工艺中，主要包括如下几个步骤：硅刻蚀、硅通孔绝缘层沉积、硅通孔绝缘层底部刻蚀，硅通孔金属填充(沉积阻挡层、种子层、电镀Cu填充)等。其中，硅通孔的干法刻蚀过程中仍存在如下问题：在硅通孔刻蚀工艺中，由于硅通孔底部存在绝缘层(材料通常为无机绝缘材料，例如SiO2、SiN等)，此绝缘层会造成刻蚀过程中电荷在绝缘层表面上积聚而产生电场，进而引起刻蚀性离子的方向在电场作用下发生横向偏转产生硅横向刻蚀(也称为notching)，即，积聚的电荷会增加离子刻蚀绝缘层上方硅通孔两侧的硅材质构成的衬底。这种现象会导致后续硅通孔填充产生空洞，进而会造成漏电流变大等问题，影响硅通孔的电学性能。A through silicon via (TSV), also known as a through silicon via, is a vertical interconnect that penetrates a silicon wafer or chip. TSV can be used to realize 3D integrated circuit packaging, for example, TSV can stack multiple chips to realize chip or circuit interconnection. At present, in the traditional process of etching TSVs, it mainly includes the following steps: silicon etching, TSV insulating layer deposition, TSV insulating layer bottom etching, TSV metal filling (depositing barrier layer, seed layer, electroplating Cu fill), etc. Among them, the following problems still exist in the dry etching process of TSVs: in the TSVs etching process, since there is an insulating layer (the material is usually an inorganic insulating material, such as SiO2, SiN, etc.) at the bottom of the TSVs, this The insulating layer will cause the charge to accumulate on the surface of the insulating layer during the etching process to generate an electric field, which will cause the direction of the etchant ions to be laterally deflected under the action of the electric field to produce silicon lateral etching (also known as notching), that is, the accumulated The charge build-up ions etch the silicon substrate on both sides of the TSV above the insulating layer. This phenomenon will lead to voids in subsequent through-silicon via filling, which will cause problems such as increased leakage current and affect the electrical performance of the through-silicon vias.

因此，如何减小或避免硅通孔的刻蚀过程中硅横向刻蚀，是亟待解决的问题。Therefore, how to reduce or avoid silicon lateral etching during the etching process of the TSVs is an urgent problem to be solved.

发明内容Contents of the invention

本申请实施例提供一种半导体装置以及半导体装置的制作方法，以减小或避免因为电荷堆积，造成的硅通孔刻蚀过程中硅横向刻蚀。Embodiments of the present application provide a semiconductor device and a manufacturing method of the semiconductor device, so as to reduce or avoid lateral etching of silicon during the etching process of through-silicon vias caused by charge accumulation.

第一方面，本申请实施例提供了一种半导体装置，包括：In a first aspect, an embodiment of the present application provides a semiconductor device, including:

第一芯片，所述第一芯片包括依次层叠的第一衬底、第一互连层和具有第一开口的第一绝缘层，所述第一互连层包括第二绝缘层和第一电连接层；所述第一开口暴露出所述第一电连接层，所述第一绝缘层为无机绝缘材料。A first chip, the first chip includes a first substrate, a first interconnection layer and a first insulating layer with a first opening stacked in sequence, the first interconnection layer includes a second insulating layer and a first electrical A connection layer; the first opening exposes the first electrical connection layer, and the first insulating layer is an inorganic insulating material.

第二芯片，所述第二芯片包括依次层叠的第二衬底、第二互连层和第三绝缘层，所述第二互连层包括第四绝缘层和第二电连接层，其中，所述第二芯片以背对的方式层叠在所述第一绝缘层上。The second chip, the second chip includes a second substrate, a second interconnection layer and a third insulating layer stacked in sequence, the second interconnection layer includes a fourth insulating layer and a second electrical connection layer, wherein, The second chips are laminated on the first insulating layer in a back-to-back manner.

第三互连层，所述第三互连层包括第五绝缘层和第三电连接层，所述第三互连层层叠于所述第二芯片远离所述第一芯片一侧。A third interconnection layer, the third interconnection layer includes a fifth insulating layer and a third electrical connection layer, and the third interconnection layer is stacked on a side of the second chip away from the first chip.

硅通孔，所述硅通孔包括相连的第一段硅通孔和第二段硅通孔，所述第二段硅通孔在所述第一衬底上的投影覆盖所述第一段硅通孔在所述第一衬底上的投影；所述第一段硅通孔位于所述第一开口中，所述第一段硅通孔的底部连接所述第一电连接层；所述第二段硅通孔贯穿所述第二芯片，所述第二段硅通孔的底部连接所述第一段硅通孔，顶部连接所述第三电连接层。through-silicon vias, the through-silicon vias include a connected first section of through-silicon vias and a second section of through-silicon vias, and the projection of the second section of through-silicon vias on the first substrate covers the first section The projection of the through-silicon via on the first substrate; the first section of the through-silicon via is located in the first opening, and the bottom of the first section of the through-silicon via is connected to the first electrical connection layer; The second TSV runs through the second chip, the bottom of the second TSV is connected to the first TSV, and the top is connected to the third electrical connection layer.

本申请第一方面实施例提供的半导体装置中硅通孔包括相连的两个部分，分别是第一段硅通孔和第二段硅通孔。其中，第一段硅通孔位于第一芯片的第一开口处，该第一开口是在第一绝缘层表面暴露出第一电连接层的开口，由于该第一开口底部暴露有第一电连接层，且 第一电连接层电导率较高，所以在干法刻蚀过程中，电荷不会大量堆积在开口底部，避免了电荷在开口底部积聚而产生电场，从而大大的减小了横向刻蚀的现象；而且，在干法刻蚀过程中，同等电荷刻蚀绝缘材料的难度要大于刻蚀硅材料的难度，因此，在第一开口位于绝缘层的情况下，即，第一开口的两侧是绝缘层的情况下，会进一步的减小电荷横向刻蚀的现象，在后续硅通孔填充时，也不会产生空洞。第二段硅通孔是贯穿第二芯片的硅通孔，由于第二段硅通孔的底部连接第一段硅通孔，所以在刻蚀第二段硅通孔的过程中，第二段硅通孔对应开口的底部会连接第一开口，进而，第二段硅通孔对应的开口底部也不会存在电荷堆积，进而减小或避免了横向刻蚀现象。另外，本申请实施例中第一段硅通孔要小于第二段硅通孔，即，第二段硅通孔在所述第一衬底上的投影覆盖所述第一段硅通孔在所述第一衬底上的投影，以便在制备第一段硅通孔和第二段硅通孔时，不易产生空洞，避免了漏电流变大的问题，保障了半导体装置的性能。The through-silicon via in the semiconductor device provided by the embodiment of the first aspect of the present application includes two connected parts, which are the first section of the through-silicon via and the second section of the through-silicon via. Wherein, the first section of TSV is located at the first opening of the first chip, and the first opening is an opening that exposes the first electrical connection layer on the surface of the first insulating layer. connection layer, and the conductivity of the first electrical connection layer is relatively high, so during the dry etching process, a large amount of charges will not accumulate at the bottom of the opening, which avoids the electric field generated by the accumulation of charges at the bottom of the opening, thereby greatly reducing the lateral The phenomenon of etching; moreover, in the dry etching process, the difficulty of etching the insulating material with the same charge is greater than the difficulty of etching the silicon material. Therefore, in the case where the first opening is located in the insulating layer, that is, the first opening In the case where both sides are insulating layers, the phenomenon of charge lateral etching will be further reduced, and voids will not be generated when the subsequent through-silicon vias are filled. The second TSV is a TSV that runs through the second chip. Since the bottom of the second TSV is connected to the first TSV, in the process of etching the second TSV, the second TSV The bottom of the opening corresponding to the TSV is connected to the first opening, and furthermore, there is no charge accumulation at the bottom of the opening corresponding to the second TSV, thereby reducing or avoiding the lateral etching phenomenon. In addition, in the embodiment of the present application, the first section of TSVs is smaller than the second section of TSVs, that is, the projection of the second section of TSVs on the first substrate covers the first section of TSVs. The projection on the first substrate is not easy to generate voids when preparing the first through-silicon via and the second through-silicon via, avoiding the problem of increased leakage current and ensuring the performance of the semiconductor device.

在一种可能实现的方式中，所述第一段硅通孔的第一端连接所述第二段硅通孔的第二端，且第二端所在的区域覆盖第一端所在的区域，其中，所述第一端为所述第一段硅通孔的且远离第一电连接层的一端，所述第二端为第二段硅通孔的且靠近所述第一绝缘层的一端。在本申请实施例中，第二端所在的区域覆盖第一端所在的区域，即，所述第一段硅通孔要小于第二段硅通孔，以便在后续第一段硅通孔和第二段硅通孔填充时，不易产生空洞，避免了漏电流变大的问题，保障了半导体装置的性能。In a possible implementation manner, the first end of the first TSV is connected to the second end of the second TSV, and the area where the second end is located covers the area where the first end is located, Wherein, the first end is an end of the first section of TSV and away from the first electrical connection layer, and the second end is an end of the second section of TSV close to the first insulating layer . In the embodiment of the present application, the area where the second end is located covers the area where the first end is located, that is, the first section of TSVs is smaller than the second section of TSVs, so that the subsequent first section of TSVs and TSVs When the second TSV is filled, it is not easy to generate voids, which avoids the problem of increased leakage current and ensures the performance of the semiconductor device.

在一种可能实现的方式中，在垂直于所述第一衬底的方向上，所述第一绝缘层厚度大于0微米小于或等于2微米。在本申请实施例中，随着第一绝缘层厚度的增加，在刻蚀过程中可以逐渐减小电荷堆积所产生的电场对刻蚀性离子方向的影响，从而减小或避免横向刻蚀现象。In a possible implementation manner, in a direction perpendicular to the first substrate, the thickness of the first insulating layer is greater than 0 micrometers and less than or equal to 2 micrometers. In the embodiment of the present application, as the thickness of the first insulating layer increases, the influence of the electric field generated by the charge accumulation on the direction of the etching ions can be gradually reduced during the etching process, thereby reducing or avoiding the lateral etching phenomenon .

在一种可能实现的方式中，所述第一电连接层的材质包括铜；所述装置还包括设置于所述第一开口处的刻蚀停止层，所述刻蚀停止层的底部连接所述第一电连接层，顶部连接所述第一段硅通孔。目前，在刻蚀硅通孔底部绝缘层过程中，即第一开口的刻蚀过程中为了将底部电连接层充分露出，通常会进行过刻蚀(over etch)步骤。当底部电连接层为铜Cu时，过刻蚀会导致Cu反溅射到硅通孔侧壁上，对硅通孔侧壁造成Cu污染，会引起硅通孔的击穿电压降低从而对整个硅通孔的电学性能产生负面影响。因此，在本申请实施例中，在第一电连接层的材质为铜的情况下，在所述第一开口处还包括刻蚀停止层，该刻蚀停止层可以在过刻蚀防止铜溅射，保证该硅通孔的性能。In a possible implementation manner, the material of the first electrical connection layer includes copper; the device further includes an etching stop layer disposed at the first opening, the bottom of the etching stop layer is connected to the The first electrical connection layer, the top of which is connected to the first section of TSVs. At present, in the process of etching the insulating layer at the bottom of the TSV, that is, during the etching process of the first opening, in order to fully expose the bottom electrical connection layer, an over etch step is usually performed. When the bottom electrical connection layer is copper Cu, over-etching will cause Cu back-sputtering to the sidewall of the TSV, causing Cu pollution to the sidewall of the TSV, which will cause the breakdown voltage of the TSV to decrease, thereby affecting the entire TSV. The electrical performance of TSVs is negatively affected. Therefore, in the embodiment of the present application, in the case that the material of the first electrical connection layer is copper, an etching stop layer is further included at the first opening, and the etching stop layer can prevent copper splashing during over-etching. radiation to ensure the performance of the TSV.

在一种可能实现的方式中，在垂直于所述第一衬底方向上，所述刻蚀停止层厚度小于所述第一开口的深度。在本申请实施例中，为了保证硅通孔的电学性能，刻蚀停止层的厚度要小于形成第一段硅通孔的第一开口的深度。In a possible implementation manner, in a direction perpendicular to the first substrate, the thickness of the etching stop layer is smaller than the depth of the first opening. In the embodiment of the present application, in order to ensure the electrical performance of the through-silicon via, the thickness of the etching stop layer is smaller than the depth of the first opening forming the first section of the through-silicon via.

在一种可能实现的方式中，所述刻蚀停止层的材质包括Ni、NiMoP、NiP、NiB、Co、CoWP、Ti、Ta、TiN、TaN、TiW、Al、Cr、W、Mn或Mg中的一种。在本申请实施例中，刻蚀停止层的材质一般选择具有导电性能，且不会因为过刻蚀出现反溅射问题的金属。包括但不限于以下材质中的一种：Ni、NiMoP、NiP、NiB、Co、CoWP、Ti、Ta、TiN、TaN、TiW、Al、Cr、W、Mn、Mg。In a possible implementation manner, the material of the etching stop layer includes Ni, NiMoP, NiP, NiB, Co, CoWP, Ti, Ta, TiN, TaN, TiW, Al, Cr, W, Mn or Mg kind of. In the embodiment of the present application, the material of the etching stop layer is generally selected to be a metal that has conductive properties and does not cause anti-sputtering problems due to over-etching. Including but not limited to one of the following materials: Ni, NiMoP, NiP, NiB, Co, CoWP, Ti, Ta, TiN, TaN, TiW, Al, Cr, W, Mn, Mg.

在一种可能实现的方式中，所述装置还包括非晶硅键合层，所述非晶硅键合层设置于所述第二衬底与所述第一绝缘层之间。在本申请实施例中，除了第一芯片和第二芯片直接键合的方式，还可以通过如：非晶硅键合层、绝缘键合层等其他方式键合连接。In a possible implementation manner, the device further includes an amorphous silicon bonding layer, and the amorphous silicon bonding layer is disposed between the second substrate and the first insulating layer. In the embodiment of the present application, in addition to the direct bonding of the first chip and the second chip, other methods such as an amorphous silicon bonding layer, an insulating bonding layer, and the like may also be used for bonding connection.

在一种可能实现的方式中，在垂直与所述第一衬底方向上，所述第一衬底的厚度大于所 述第二衬底的厚度。在本申请实施例中，可以根据业务需求减薄第二芯片中第二衬底的厚度，以提高硅通孔的电学性能以及减小半导体装置的体积。In a possible implementation manner, in a direction perpendicular to the first substrate, the thickness of the first substrate is greater than the thickness of the second substrate. In the embodiment of the present application, the thickness of the second substrate in the second chip can be reduced according to business requirements, so as to improve the electrical performance of the TSV and reduce the volume of the semiconductor device.

在一种可能实现的方式中，在垂直于所述第二衬底方向上，所述第二衬底的厚度大于或等于5微米且小于或等于100微米。在本申请实施例中，由于第二衬底中还可能制作有晶体管等有源器件，所以可以根据业务需求，第二衬底的厚度在5μm-100μm之间。另外，减薄第二衬底的厚度可以提高硅通孔的电学性能以及减小半导体装置的体积。In a possible implementation manner, in a direction perpendicular to the second substrate, the thickness of the second substrate is greater than or equal to 5 microns and less than or equal to 100 microns. In the embodiment of the present application, since active devices such as transistors may also be fabricated in the second substrate, the thickness of the second substrate may be between 5 μm and 100 μm according to business requirements. In addition, reducing the thickness of the second substrate can improve the electrical performance of the TSV and reduce the volume of the semiconductor device.

在一种可能实现的方式中，所述第三绝缘层中嵌设有第一金属通孔，所述第一金属通孔的底部连接所述第二电连接层，顶部连接所述第三电连接层；其中，所述第一电连接层和所述第二电连接层通过所述硅通孔、所述第一金属通孔和所述第三电连接层形成电连接。在本申请实施例中，半导体装置的第一电连接层和所述第二电连接层通过所述硅通孔、所述第一金属通孔和所述第三电连接层形成电连接。In a possible implementation manner, a first metal via is embedded in the third insulating layer, the bottom of the first metal via is connected to the second electrical connection layer, and the top is connected to the third electrical connection layer. A connection layer; wherein, the first electrical connection layer and the second electrical connection layer are electrically connected through the through-silicon via, the first metal through-hole and the third electrical connection layer. In the embodiment of the present application, the first electrical connection layer of the semiconductor device is electrically connected to the second electrical connection layer through the through-silicon via, the first through-metal via and the third electrical connection layer.

在一种可能实现的方式中，所述装置还包括：In a possible implementation manner, the device further includes:

具有第二开口的第六绝缘层，所述第六绝缘层层叠在所述第三互连层远离所述第二芯片的一侧，所述第二开口暴露出所述第三电连接层。A sixth insulating layer with a second opening, the sixth insulating layer is stacked on the side of the third interconnection layer away from the second chip, the second opening exposes the third electrical connection layer.

第三芯片，所述第三芯片包括依次层叠的第三衬底、第四互连层和第七绝缘层，所述第四互连层包括第八绝缘层和第四电连接层；其中，所述第三芯片以背对的方式层叠在所述第六绝缘层远离所述第三互连层的一侧。The third chip, the third chip includes a third substrate, a fourth interconnection layer and a seventh insulating layer stacked in sequence, and the fourth interconnection layer includes an eighth insulating layer and a fourth electrical connection layer; wherein, The third chip is stacked on the side of the sixth insulating layer away from the third interconnection layer in a back-to-back manner.

第五互连层，所述第五互连层包括第九绝缘层和第五电连接层，所述第五互连层层叠在所述第三芯片远离所述第六绝缘层的一侧。A fifth interconnection layer, the fifth interconnection layer including a ninth insulating layer and a fifth electrical connection layer, the fifth interconnection layer stacked on a side of the third chip away from the sixth insulating layer.

所述硅通孔还包括相连的第三段硅通孔和第四段硅通孔，所述第四段硅通孔在所述第一衬底上的投影覆盖所述第三段硅通孔在所述第二衬底上的投影；所述第三段硅通孔位于所述第二开口中，所述第三段硅通孔的底部连接所述第三电连接层；所述第四段硅通孔贯穿所述第三芯片，所述第四段硅通孔的底部连接所述第三段硅通孔，顶部连接所述第五电连接层。The TSV further includes a connected third TSV and a fourth TSV, and the projection of the fourth TSV on the first substrate covers the third TSV Projection on the second substrate; the third through-silicon via is located in the second opening, and the bottom of the third through-silicon via is connected to the third electrical connection layer; the fourth A section of through-silicon vias runs through the third chip, a bottom of the fourth section of through-silicon vias is connected to the third section of through-silicon vias, and a top is connected to the fifth electrical connection layer.

所述第八绝缘层中包括第二金属通孔，所述第二金属通孔的底部连接所述第四电连接层，顶部连接所述第五电连接层；其中，所述第一电连接层、所述第二电连接层和第四电连接层通过所述硅通孔、所述第一金属通孔、所述第二金属通孔、所述第三电连接层和所述第五电连接层形成电连接。The eighth insulating layer includes a second metal via, the bottom of the second metal via is connected to the fourth electrical connection layer, and the top is connected to the fifth electrical connection layer; wherein the first electrical connection layer, the second electrical connection layer and the fourth electrical connection layer through the silicon via, the first metal via, the second metal via, the third electrical connection layer and the fifth The electrical connection layer forms electrical connections.

在本申请实施例中，该半导体装置不仅仅可以堆叠两个芯片，还可以根据业务需求，通过上述方式堆叠两个以上的芯片。例如：本申请实施例的半导体装置中，可以实现第一芯片、第二芯片和第三芯片的堆叠。其中，在将第三芯片堆叠在第二芯片上时，为保证硅通孔不会因空隙影响硅通孔的电学性能，可以先刻蚀硅通孔底部绝缘层开口，减小或避免电荷堆积。同理，本申请实施例并不限制芯片堆叠的个数，可以根据业务需求，实现多层堆叠。In the embodiment of the present application, the semiconductor device can not only stack two chips, but also can stack more than two chips in the above-mentioned manner according to business requirements. For example: in the semiconductor device of the embodiment of the present application, stacking of the first chip, the second chip and the third chip can be realized. Wherein, when the third chip is stacked on the second chip, in order to ensure that the electrical performance of the TSV will not be affected by the gap, the insulating layer opening at the bottom of the TSV can be etched first to reduce or avoid charge accumulation. Similarly, the embodiment of the present application does not limit the number of chip stacks, and multi-layer stacking can be realized according to business requirements.

第二方面，本申请实施例提供了一种半导体装置的制作方法，可包括：In a second aspect, the embodiment of the present application provides a method for manufacturing a semiconductor device, which may include:

步骤一，提供第一芯片，所述第一芯片包括依次层叠的第一衬底、第一互连层和第一绝缘层，所述第一互连层包括第二绝缘层和第一电连接层； Step 1, providing a first chip, the first chip includes a first substrate, a first interconnection layer, and a first insulating layer stacked in sequence, and the first interconnection layer includes a second insulating layer and a first electrical connection layer;

步骤二，对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，所述第一绝缘层为无机绝缘材料； Step 2, etching the first insulating layer, forming a first opening exposing the first electrical connection layer on the surface of the first insulating layer, and the first insulating layer is an inorganic insulating material;

步骤三，提供第二芯片，所述第二芯片包括依次层叠的第二衬底、第二互连层和第三绝缘层，所述第二互连层包括第四绝缘层和第二电连接层； Step 3, providing a second chip, the second chip includes a second substrate, a second interconnection layer, and a third insulating layer stacked in sequence, and the second interconnection layer includes a fourth insulating layer and a second electrical connection layer;

步骤四，将所述第一芯片与所述第二芯片键合，其中，所述第二芯片以背对的方式层叠 在所述第一绝缘层上； Step 4, bonding the first chip to the second chip, wherein the second chip is laminated on the first insulating layer in a back-to-back manner;

步骤五，在所述第一绝缘层的所述第一开口对应的位置，对键合后的所述第二芯片进行刻蚀，在所述第二芯片表面形成暴露出所述第一开口的第三开口；Step 5: Etching the bonded second chip at the position corresponding to the first opening of the first insulating layer, forming a hole on the surface of the second chip exposing the first opening. third opening;

步骤六，在所述第一开口处和所述第三开口处形成硅通孔。Step six, forming through-silicon vias at the first opening and the third opening.

本申请第一方面实施例提供半导体装置的制作方法中，需要制作的硅通孔包括相连的两个部分，分别是第一段硅通孔和第二段硅通孔。其中，第一段硅通孔位于第一芯片的第一开口处，该第一开口是在第一绝缘层表面暴露出第一电连接层的开口，由于该第一开口底部暴露有第一电连接层，且第一电连接层电导率较高，所以在干法刻蚀过程中，电荷不会大量堆积在开口底部，避免了电荷在开口底部积聚而产生电场，从而大大的减小了横向刻蚀的现象；而且，在干法刻蚀过程中，同等电荷刻蚀绝缘材料的难度要大于刻蚀硅材料的难度，因此，在第一开口位于绝缘层的情况下，即，第一开口的两侧是绝缘层的情况下，会进一步的减小电荷横向刻蚀的现象，在后续硅通孔填充时，也不会产生空洞。第二段硅通孔是贯穿第二芯片的硅通孔，由于第二段硅通孔的底部连接第一段硅通孔，所以在刻蚀第二段硅通孔的过程中，第二段硅通孔对应开口的底部会连接第一开口，进而，第二段硅通孔对应的开口底部也不会存在电荷堆积，进而减小或避免了横向刻蚀现象。另外，由于所述第一段硅通孔的顶部区域在所述第二段硅通孔的底部区域中。即，第一段硅通孔要小于第二段硅通孔，所以在后续第一段硅通孔和第二段硅通孔填充时，不易产生空洞，避免了漏电流变大的问题，保障了半导体装置的电学性能。In the embodiment of the first aspect of the present application, in the method for manufacturing a semiconductor device, the through-silicon via to be fabricated includes two connected parts, which are the first section of the through-silicon via and the second section of the through-silicon via. Wherein, the first section of TSV is located at the first opening of the first chip, and the first opening is an opening that exposes the first electrical connection layer on the surface of the first insulating layer. connection layer, and the conductivity of the first electrical connection layer is relatively high, so during the dry etching process, a large amount of charges will not accumulate at the bottom of the opening, which avoids the electric field generated by the accumulation of charges at the bottom of the opening, thereby greatly reducing the lateral The phenomenon of etching; moreover, in the dry etching process, the difficulty of etching the insulating material with the same charge is greater than the difficulty of etching the silicon material. Therefore, in the case where the first opening is located in the insulating layer, that is, the first opening In the case where both sides are insulating layers, the phenomenon of charge lateral etching will be further reduced, and voids will not be generated when the subsequent through-silicon vias are filled. The second TSV is a TSV that runs through the second chip. Since the bottom of the second TSV is connected to the first TSV, in the process of etching the second TSV, the second TSV The bottom of the opening corresponding to the TSV is connected to the first opening, and furthermore, there is no charge accumulation at the bottom of the opening corresponding to the second TSV, thereby reducing or avoiding the lateral etching phenomenon. In addition, since the top region of the first TSV is in the bottom region of the second TSV. That is, the first TSV is smaller than the second TSV, so when the first TSV and the second TSV are subsequently filled, it is not easy to generate voids, which avoids the problem of increased leakage current and ensures electrical performance of semiconductor devices.

在一种可能实现的方式中，在垂直于所述第一衬底的方向上，所述第一绝缘层厚度大于0微米小于或等于2微米。在本申请实施例中，由于厚度的增加，在刻蚀过程中可以进一步的减小电荷堆积所产生的电场对刻蚀性离子方向的影响，从而减小或避免横向刻蚀现象。In a possible implementation manner, in a direction perpendicular to the first substrate, the thickness of the first insulating layer is greater than 0 micrometers and less than or equal to 2 micrometers. In the embodiment of the present application, due to the increase of the thickness, the influence of the electric field generated by charge accumulation on the direction of the etching ions can be further reduced during the etching process, thereby reducing or avoiding the lateral etching phenomenon.

在一种可能实现的方式中，所述第一电连接层的材质包括铜；所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，步骤之后还包括：在所述第一绝缘层的所述第一开口内的所述第一电连接层上形成刻蚀停止层，其中，在垂直于所述第一衬底方向上，所述刻蚀停止层厚度小于所述第一开口的深度。采用的工艺可以是选择性沉积工艺，例如化学镀；也可以采用物理气相沉积和刻蚀的方法。In a possible implementation manner, the material of the first electrical connection layer includes copper; the etching of the first insulating layer is formed on the surface of the first insulating layer to expose the first electrical connection layer. The first opening of the connection layer, after the step, further includes: forming an etch stop layer on the first electrical connection layer in the first opening of the first insulating layer, wherein, when perpendicular to the first In the direction of the substrate, the thickness of the etching stop layer is smaller than the depth of the first opening. The process used may be a selective deposition process, such as chemical plating; physical vapor deposition and etching methods may also be used.

在一种可能实现的方式中，所述第一芯片包括依次层叠的第一衬底、第一互连层、刻蚀停止层和第一绝缘层，所述刻蚀停止层嵌于第一绝缘层，底部覆盖部分或全部第一电连接层、顶部连接第一绝缘层；所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口步骤，包括：对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出与所述第一电连接层连接的所述刻蚀停止层的第一开口。在本申请实施例中，在第一电连接层的材质为铜的情况下，在所述第一开口处还包括刻蚀停止层，该刻蚀停止层可以在过刻蚀防止铜溅射，保证该硅通孔的性能。In a possible implementation manner, the first chip includes a first substrate, a first interconnect layer, an etch stop layer, and a first insulating layer stacked in sequence, and the etch stop layer is embedded in the first insulating layer. Layer, the bottom covers part or all of the first electrical connection layer, and the top is connected to the first insulating layer; the first insulating layer is etched to expose the first electrical connection on the surface of the first insulating layer The step of opening the first layer includes: etching the first insulating layer, forming a first layer on the surface of the first insulating layer exposing the etching stop layer connected to the first electrical connection layer. Open your mouth. In the embodiment of the present application, when the material of the first electrical connection layer is copper, an etching stop layer is further included at the first opening, and the etching stop layer can prevent copper sputtering during over-etching, The performance of the TSV is guaranteed.

在一种可能实现的方式中，所述刻蚀停止层的材质包括Ni、NiMoP、NiP、NiB、Co、CoWP、Ti、Ta、TiN、TaN、TiW、Al、Cr、W、Mn或Mg中的一种。In a possible implementation manner, the material of the etching stop layer includes Ni, NiMoP, NiP, NiB, Co, CoWP, Ti, Ta, TiN, TaN, TiW, Al, Cr, W, Mn or Mg kind of.

在一种可能实现的方式中，所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，步骤之前还包括：在所述第一绝缘层表面上沉积覆盖非晶硅键合层；所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口的步骤，包括：对所述第一绝缘层和所述非晶硅键合层进行刻蚀，在所述非晶硅键合层表面形成暴露出所述第一电连接层的所述第一开口。在本申请实施例中，第一芯片和第二芯片还可以通过如：非晶硅键合层、绝缘键合层等键合层的方式键合连接， 以降低键合工艺温度。例如：在通过非晶硅键合层连接第一芯片和第二芯片时，可以在第一绝缘层表面上沉积覆盖非晶硅键合层后，刻蚀第一绝缘层和非晶硅键合层，并在非晶硅键合层表面形成第一开口。In a possible implementation manner, before the step of etching the first insulating layer and forming a first opening exposing the first electrical connection layer on the surface of the first insulating layer, the step further includes: Depositing an amorphous silicon bonding layer on the surface of the first insulating layer; etching the first insulating layer to form a layer on the surface of the first insulating layer exposing the first electrical connection layer The first opening step includes: etching the first insulating layer and the amorphous silicon bonding layer, and forming the exposed first electrical connection layer on the surface of the amorphous silicon bonding layer. Describe the first opening. In the embodiment of the present application, the first chip and the second chip may also be bonded and connected through a bonding layer such as an amorphous silicon bonding layer, an insulating bonding layer, etc., so as to reduce a bonding process temperature. For example: when connecting the first chip and the second chip through the amorphous silicon bonding layer, after depositing the covering amorphous silicon bonding layer on the surface of the first insulating layer, etch the first insulating layer and the amorphous silicon bonding layer, and form a first opening on the surface of the amorphous silicon bonding layer.

在一种可能实现的方式中，所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，步骤之后还包括：在所述第一绝缘层表面上沉积覆盖非晶硅键合层；在垂直于所述第一衬底方向上，所述非晶硅键合层的厚度大于所述第一开口的深度时，对所述非晶硅键合层进行抛光直至所述非晶硅键合层的表面与所述第一衬底表面平齐。在本申请实施例中，除了第一芯片和第二芯片直接键合的方式，还可以通过如：非晶硅键合层、绝缘键合层等其他方式键合连接。例如：可以在第一绝缘层刻蚀出第一开口后，再沉积非晶硅键合层。当沉积的非晶硅键合层的厚度大于第一开口的深度时，还可以通过化学机械抛光进行非晶硅键合层表面平坦化。In a possible implementation manner, after the step of etching the first insulating layer and forming a first opening exposing the first electrical connection layer on the surface of the first insulating layer, the step further includes: depositing an amorphous silicon bonding layer covering the surface of the first insulating layer; in a direction perpendicular to the first substrate, when the thickness of the amorphous silicon bonding layer is greater than the depth of the first opening, Polishing the amorphous silicon bonding layer until the surface of the amorphous silicon bonding layer is flush with the surface of the first substrate. In the embodiment of the present application, in addition to the direct bonding of the first chip and the second chip, other methods such as an amorphous silicon bonding layer, an insulating bonding layer, and the like may also be used for bonding connection. For example, the amorphous silicon bonding layer may be deposited after the first opening is etched in the first insulating layer. When the thickness of the deposited amorphous silicon bonding layer is greater than the depth of the first opening, the surface of the amorphous silicon bonding layer can also be planarized by chemical mechanical polishing.

在一种可能实现的方式中，所述在所述第一绝缘层的所述第一开口对应的位置，对键合后的所述第二芯片进行刻蚀，在所述第二芯片表面形成暴露出所述第一开口的第三开口，步骤之后还包括：在所述第一绝缘层的所述第一开口对应的位置，对所述非晶硅键合层进行刻蚀，暴露出所述第一电连接层。在本申请实施例中，沉积非晶硅键合层后，还需要刻蚀第一开口底部的非晶硅键合层，以便暴露出开口底部连接的第一电连接层，以形成电连接。In a possible implementation manner, at the position corresponding to the first opening of the first insulating layer, the bonded second chip is etched to form a Exposing the third opening of the first opening, after the step, further includes: etching the amorphous silicon bonding layer at the position corresponding to the first opening of the first insulating layer to expose the The first electrical connection layer. In the embodiment of the present application, after depositing the amorphous silicon bonding layer, the amorphous silicon bonding layer at the bottom of the first opening needs to be etched to expose the first electrical connection layer connected to the bottom of the opening to form an electrical connection.

在一种可能实现的方式中，所述提供第二芯片，步骤之后还包括：以所述第二衬底背面向上的方式，将所述第二芯片临时键合至支撑基板，并对所述第二衬底背面进行减薄；所述将所述第一芯片与所述第二芯片键合的步骤，包括：通过所述支撑基板，向所述第一衬底正面方向，将所述第二芯片的所述第二衬底背面与所述第一芯片的所述第一绝缘层或所述非晶硅键合层进行直接键合；去除所述支撑基板。为了方便减薄第二衬底，可以先将第二芯片临时键合至支撑基板，而且该方式可以便于将第二芯片的第二衬底背面与第一绝缘层进行直接键合。另外，减薄第二衬底的厚度可以提高硅通孔的电学性能以及减小半导体装置的体积。In a possible implementation manner, after the step of providing the second chip, the step further includes: temporarily bonding the second chip to the supporting substrate with the back of the second substrate facing up, and attaching the second chip to the support substrate. The back side of the second substrate is thinned; the step of bonding the first chip to the second chip includes: passing the supporting substrate toward the front side of the first substrate, and bonding the first chip to the front side of the first substrate The back surface of the second substrate of the second chip is directly bonded to the first insulating layer or the bonding layer of amorphous silicon of the first chip; and the supporting substrate is removed. In order to facilitate the thinning of the second substrate, the second chip can be temporarily bonded to the supporting substrate first, and this method can facilitate direct bonding of the back surface of the second substrate of the second chip to the first insulating layer. In addition, reducing the thickness of the second substrate can improve the electrical performance of the TSV and reduce the volume of the semiconductor device.

在一种可能实现的方式中，在垂直于所述第二衬底方向上，所述第二衬底的厚度大于或等于5微米且小于或等于100微米。在本申请实施例中，由于第二衬底中还可能制作有晶体管等有源器件，所以可以根据业务需求，第二衬底的厚度在5μm-100μm之间。另外，减薄第二衬底的厚度可以提高硅通孔的电学性能以及减小半导体装置的体积。In a possible implementation manner, in a direction perpendicular to the second substrate, the thickness of the second substrate is greater than or equal to 5 microns and less than or equal to 100 microns. In the embodiment of the present application, since active devices such as transistors may also be fabricated in the second substrate, the thickness of the second substrate may be between 5 μm and 100 μm according to business requirements. In addition, reducing the thickness of the second substrate can improve the electrical performance of the TSV and reduce the volume of the semiconductor device.

在一种可能实现的方式中，所述硅通孔包括相连的第一段硅通孔和第二段硅通孔；所述第一段硅通孔为所述第一开口处形成的硅通孔，所述第一段硅通孔的底部为所述第一电连接层；所述第二段硅通孔为所述第三开口处形成的硅通孔，贯穿所述第二芯片，所述第二段硅通孔的底部连接所述第一段硅通孔，顶部连接所述第三电连接层。In a possible implementation manner, the TSV includes a first section of TSV and a second section of TSV connected; the first section of TSV is a TSV formed at the first opening. holes, the bottom of the first section of through-silicon vias is the first electrical connection layer; the second section of through-silicon vias is a through-silicon via formed at the third opening, passing through the second chip, so The bottom of the second TSV is connected to the first TSV, and the top is connected to the third electrical connection layer.

在一种可能实现的方式中，所述第一段硅通孔的第一端连接所述第二段硅通孔的第二端，且第二端所在的区域覆盖第一端所在的区域；第一端为所述第一段硅通孔远离第一电连接层的一端，第二端为第二段硅通孔靠近第一绝缘层的一端。在本申请实施例中，第二端所在的区域覆盖第一端所在的区域，即，所述第一段硅通孔要小于第二段硅通孔，以便在后续第一段硅通孔和第二段硅通孔填充时，不易产生空洞，避免了漏电流变大的问题，保障了半导体装置的性能。In a possible implementation manner, the first end of the first section of TSV is connected to the second end of the second section of TSV, and the area where the second end is located covers the area where the first end is located; The first end is an end of the first TSV away from the first electrical connection layer, and the second end is an end of the second TSV close to the first insulating layer. In the embodiment of the present application, the area where the second end is located covers the area where the first end is located, that is, the first section of TSVs is smaller than the second section of TSVs, so that the subsequent first section of TSVs and TSVs When the second TSV is filled, it is not easy to generate voids, which avoids the problem of increased leakage current and ensures the performance of the semiconductor device.

在一种可能实现的方式中，所述第一开口暴露出部分所述第一电连接层；所述第二开口暴露出部分所述第三电连接层。In a possible implementation manner, the first opening exposes part of the first electrical connection layer; the second opening exposes part of the third electrical connection layer.

在一种可能实现的方式中，所述在所述第一开口处和所述第三开口处形成硅通孔，步骤之后还包括：对所述第三绝缘层进行刻蚀并填充第一导电材料，形成第一金属通孔，所述第 一金属通孔的底部连接所述第二电连接层，顶部连接所述第三电连接层；在键合后的所述第二芯片远离所述第一芯片的一侧形成第三互连层，所述第三互连层包括第五绝缘层和第三电连接层，其中，所述第一电连接层和所述第二电连接层通过所述硅通孔、所述第一金属通孔和所述第三电连接层形成电连接。In a possible implementation manner, after the step of forming through-silicon vias at the first opening and the third opening, the step further includes: etching the third insulating layer and filling the first conductive material, forming a first metal via, the bottom of the first metal via is connected to the second electrical connection layer, and the top is connected to the third electrical connection layer; after bonding, the second chip is far away from the A third interconnection layer is formed on one side of the first chip, and the third interconnection layer includes a fifth insulating layer and a third electrical connection layer, wherein the first electrical connection layer and the second electrical connection layer pass through The TSV, the first metal TSV and the third electrical connection layer are electrically connected.

在一种可能实现的方式中，所述在键合后的所述第二芯片远离所述第一芯片的一侧形成第三互连层，步骤之后还包括：在第三互连层远离所述第二芯片的一侧形成第六绝缘层，对所述第六绝缘层进行刻蚀，在所述第六绝缘层表面形成暴露出所述第三电连接层的第二开口；提供第三芯片，所述第三芯片包括依次层叠的第三衬底、第四互连层和第七绝缘层，所述第四互连层包括第八绝缘层和第四电连接层；将所述第三芯片与具有所述第二开口的所述第六绝缘层键合，其中，所述第三芯片以背对的方式层叠在所述第六绝缘层远离所述第三互连层的一侧；在所述第二开口对应的位置，对键合后的所述第三芯片进行刻蚀，在所述第三芯片表面形成暴露出所述第二开口的第四开口；在所述第二开口处和所述第四开口处形成所述硅通孔；对所述第七绝缘层进行刻蚀并填充第二导电材料形成第二金属通孔，所述第二金属通孔的底部连接所述第四电连接层，顶部连接所述第五电连接层；在键合后的所述第三芯片远离所述第六绝缘层的一侧形成第五互连层，所述第五互连层包括第九绝缘层和第五电连接层，其中，所述第一电连接层、所述第二电连接层和第四电连接层通过所述硅通孔、所述第一金属通孔、所述第二金属通孔、所述第三电连接层和所述第五电连接层形成电连接。在本申请实施例中，可以利用相同的半导体装置的制作方法制作半导体装置，该半导体装置不仅仅可以堆叠两个芯片，还可以根据业务需求，堆叠两个以上的芯片。例如，在将第三芯片堆叠在第二芯片上时，为保证硅通孔不会因空隙影响硅通孔的电学性能，可以先刻蚀硅通孔底部绝缘层开口，减小或避免电荷堆积。In a possible implementation manner, after the step of forming a third interconnect layer on the side of the bonded second chip away from the first chip, the step further includes: A sixth insulating layer is formed on one side of the second chip, and the sixth insulating layer is etched to form a second opening exposing the third electrical connection layer on the surface of the sixth insulating layer; providing a third chip, the third chip includes a third substrate, a fourth interconnection layer, and a seventh insulating layer stacked in sequence, and the fourth interconnection layer includes an eighth insulating layer and a fourth electrical connection layer; the first Three chips are bonded to the sixth insulating layer having the second opening, wherein the third chip is stacked on the side of the sixth insulating layer away from the third interconnection layer in a back-to-back manner ; at the position corresponding to the second opening, etching the bonded third chip, forming a fourth opening exposing the second opening on the surface of the third chip; forming the through-silicon hole at the opening and the fourth opening; etching the seventh insulating layer and filling it with a second conductive material to form a second metal through hole, the bottom of the second metal through hole is connected to the The fourth electrical connection layer, the top of which is connected to the fifth electrical connection layer; the fifth interconnect layer is formed on the side of the bonded third chip away from the sixth insulating layer, and the fifth interconnect The layer includes a ninth insulating layer and a fifth electrical connection layer, wherein the first electrical connection layer, the second electrical connection layer, and the fourth electrical connection layer pass through the silicon vias, the first metal vias , the second metal via, the third electrical connection layer and the fifth electrical connection layer form an electrical connection. In the embodiment of the present application, the semiconductor device can be manufactured by using the same semiconductor device manufacturing method, and the semiconductor device can not only stack two chips, but also stack more than two chips according to business requirements. For example, when the third chip is stacked on the second chip, in order to ensure that the electrical performance of the TSV will not be affected by the gap, the insulating layer opening at the bottom of the TSV can be etched first to reduce or avoid charge accumulation.

在一种可能实现的方式中，所述硅通孔还包括相连的第三段硅通孔和第四段硅通孔；所述第三段硅通孔为所述第二开口处形成的硅通孔，所述第三段硅通孔的底部连接所述第三电连接层；所述第四段硅通孔为所述第四开口处形成的硅通孔，贯穿所述第三芯片，所述第四段硅通孔的底部连接所述第三段硅通孔，顶部连接所述第五电连接层。In a possible implementation manner, the TSV further includes a connected third TSV and a fourth TSV; the third TSV is a silicon hole formed at the second opening. a through hole, the bottom of the third section of through-silicon via is connected to the third electrical connection layer; the fourth section of through-silicon via is a through-silicon via formed at the fourth opening, which runs through the third chip, The bottom of the fourth TSV is connected to the third TSV, and the top is connected to the fifth electrical connection layer.

第三方面，本申请实施例提供了一种电子设备，该电子设备包括了上述第一方面以及结合第一方面的任意一种实现方式所提供的半导体装置和电路板。该半导体装置与电路板电连接，该电子设备用于实现上述第一方面中所涉及的半导体装置的功能。In a third aspect, an embodiment of the present application provides an electronic device, which includes the first aspect and the semiconductor device and the circuit board provided in any implementation manner of the first aspect. The semiconductor device is electrically connected to the circuit board, and the electronic device is used to implement the functions of the semiconductor device in the first aspect described above.

附图说明Description of drawings

为了更清楚地说明本申请实施例或背景技术中的技术方案，下面将对本申请实施例或背景技术中所需要使用的附图进行说明。In order to more clearly illustrate the technical solutions in the embodiment of the present application or the background art, the following will describe the drawings that need to be used in the embodiment of the present application or the background art.

图1为本申请实施例提供的半导体装置制作方法的步骤流程图。FIG. 1 is a flow chart of steps of a method for manufacturing a semiconductor device provided by an embodiment of the present application.

图2是本申请实施例提供的一种第一芯片的截面图。FIG. 2 is a cross-sectional view of a first chip provided by an embodiment of the present application.

图3是本申请实施例提供的一种带有第一开口的第一芯片的截面图。Fig. 3 is a cross-sectional view of a first chip with a first opening provided by an embodiment of the present application.

图4是本申请实施例提供的一种第二芯片的截面图。FIG. 4 is a cross-sectional view of a second chip provided by an embodiment of the present application.

图5是本申请实施例提供的一种带有支撑基板的第二芯片的截面图。FIG. 5 is a cross-sectional view of a second chip with a supporting substrate provided in an embodiment of the present application.

图6是本申请实施例提供的一种键合后的第一芯片和第二芯片的截面图。FIG. 6 is a cross-sectional view of a bonded first chip and a second chip according to an embodiment of the present application.

图7是本申请实施例提供的一组带有第三开口的半导体装置的截面图。FIG. 7 is a cross-sectional view of a group of semiconductor devices with a third opening provided by an embodiment of the present application.

图8和图9是本申请实施例提供的一组带有硅通孔绝缘层的半导体装置的截面图。8 and 9 are cross-sectional views of a group of semiconductor devices with TSV insulating layers provided by the embodiments of the present application.

图10是本申请实施例提供的一种带有硅通孔的半导体装置的截面图。FIG. 10 is a cross-sectional view of a semiconductor device with TSVs provided by an embodiment of the present application.

图11是本申请实施例提供的一种带有第一金属通孔的半导体装置的截面图。FIG. 11 is a cross-sectional view of a semiconductor device with a first metal via provided by an embodiment of the present application.

图12是本申请实施例提供的一种半导体装置的截面图。FIG. 12 is a cross-sectional view of a semiconductor device provided by an embodiment of the present application.

图13是本申请实施例提供的一种带有刻蚀停止层的第一芯片的截面图。FIG. 13 is a cross-sectional view of a first chip with an etching stop layer provided by an embodiment of the present application.

图14和图15A是本申请实施例提供的一组带有刻蚀停止层的半导体装置的截面图。14 and 15A are cross-sectional views of a set of semiconductor devices with an etch stop layer provided by an embodiment of the present application.

图15B是本申请实施例提供的一组带有刻蚀停止层的半导体的截面图。FIG. 15B is a cross-sectional view of a group of semiconductors provided with an etch stop layer according to an embodiment of the present application.

图16和图17是本申请实施例提供的一组带有键合层的第一芯片的截面图。FIG. 16 and FIG. 17 are cross-sectional views of a group of first chips with bonding layers provided by the embodiment of the present application.

图18是本申请实施例提供的一种基于图17所示第一芯片的半导体装置的截面图。FIG. 18 is a cross-sectional view of a semiconductor device based on the first chip shown in FIG. 17 according to an embodiment of the present application.

图19是本申请实施例提供的一种基于图3的带有键合层的第一芯片截面图。FIG. 19 is a cross-sectional view of a first chip with a bonding layer based on FIG. 3 provided by an embodiment of the present application.

图20是本申请实施例提供的一种基于图19所示第一芯片的半导体装置的截面图。FIG. 20 is a cross-sectional view of a semiconductor device based on the first chip shown in FIG. 19 according to an embodiment of the present application.

图21是本申请实施例提供的另一种基于图3的带有键合层的第一芯片截面图。FIG. 21 is another cross-sectional view of the first chip with a bonding layer based on FIG. 3 provided by the embodiment of the present application.

图22是本申请实施例提供的一种基于图21所示第一芯片的半导体装置的截面图。FIG. 22 is a cross-sectional view of a semiconductor device based on the first chip shown in FIG. 21 according to an embodiment of the present application.

图23是本申请实施例提供的一组基于上述方式一的半导体截面图。FIG. 23 is a group of cross-sectional views of semiconductors based on the above-mentioned method 1 provided by the embodiment of the present application.

图24是本申请实施例提供的一组基于上述方式二的半导体截面图。FIG. 24 is a group of cross-sectional views of semiconductors based on the above-mentioned method 2 provided by the embodiment of the present application.

图25是本申请实施例提供的一组基于上述方式三的半导体截面图。FIG. 25 is a group of cross-sectional views of semiconductors based on the above-mentioned method 3 provided by the embodiment of the present application.

图26是本申请实施例提供的又一组半导体装置的截面图。FIG. 26 is a cross-sectional view of another group of semiconductor devices provided by the embodiment of the present application.

图27是本申请实施例提供的一种第三芯片的截面图。FIG. 27 is a cross-sectional view of a third chip provided by an embodiment of the present application.

图28是本申请实施例提供的又一组半导体装置的截面图。FIG. 28 is a cross-sectional view of another group of semiconductor devices provided by the embodiment of the present application.

图29是本申请实施例提供的又一种半导体装置的截面图。FIG. 29 is a cross-sectional view of another semiconductor device provided by an embodiment of the present application.

附图标记说明：Explanation of reference signs:

10第一芯片；10 first chips;

101第一衬底；102第一互连层；1021第二绝缘层；1022第一电连接层；103第一绝缘层；104第一开口；105刻蚀停止层；106非晶硅连接层；101 first substrate; 102 first interconnection layer; 1021 second insulating layer; 1022 first electrical connection layer; 103 first insulating layer; 104 first opening; 105 etch stop layer; 106 amorphous silicon connection layer;

20第二芯片；204支撑基板；20 second chip; 204 supporting substrate;

201第一衬底；202第一互连层；2021第四绝缘层；1022第二电连接层；203第二绝缘层；205第三开口；206硅通孔绝缘层；207硅通孔；208第一金属通孔；209第三互连层；2091第三电连接层；2092第五绝缘层；201 the first substrate; 202 the first interconnection layer; 2021 the fourth insulating layer; 1022 the second electrical connection layer; 203 the second insulating layer; 205 the third opening; The first metal via; 209 the third interconnection layer; 2091 the third electrical connection layer; 2092 the fifth insulating layer;

301第六绝缘层；302第二开口；301 sixth insulating layer; 302 second opening;

30第三芯片；30 a third chip;

401第三衬底；402第四互连层；4021第八绝缘层；4022第四电连接层；403第七绝缘层；404硅通孔；405硅通孔绝缘层；406第五互连层；4061第五电连接层；4062第九绝缘层；407第二金属通孔。401 third substrate; 402 fourth interconnection layer; 4021 eighth insulating layer; 4022 fourth electrical connection layer; 403 seventh insulating layer; 404 through silicon via; 405 through silicon via insulating layer; 406 fifth interconnection layer ; 4061 fifth electrical connection layer; 4062 ninth insulating layer; 407 second metal via.

具体实施方式Detailed ways

下面将结合本申请实施例中的附图，对本申请实施例进行描述。The embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

本申请的说明书和权利要求书及所述附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品 或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。The terms "first", "second", "third" and "fourth" in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order . Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or apparatuses.

应当理解，在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。It should be understood that in this application, "at least one (item)" means one or more, and "multiple" means two or more. "And/or" is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, "A and/or B" can mean: only A exists, only B exists, and A and B exist at the same time , where A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one item (piece) of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c ", where a, b, c can be single or multiple.

在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

首先，为了便于理解本申请实施例，以下具体分析本申请实施例所需要解决的技术问题以及应用场景。First, in order to facilitate the understanding of the embodiments of the present application, the technical problems and application scenarios to be solved by the embodiments of the present application are specifically analyzed below.

目前硅通孔(through silicon via，TSV)也称做硅穿孔，是一种穿透硅晶圆或芯片的垂直互连。TSV可用于实现3D集成电路封装，例如TSV可堆叠多片芯片，实现芯片或电路互联。在以干法刻蚀工艺制备硅通孔，主要包括如下几个步骤：硅刻蚀、硅通孔绝缘层沉积、硅通孔绝缘层底部刻蚀，硅通孔金属填充(沉积阻挡层、种子层、电镀Cu填充)等。其中，在硅通孔刻蚀工艺中，由于硅通孔底部存在绝缘层(材料通常为无机绝缘材料，例如SiO2、SiN等)，此绝缘层会造成刻蚀过程中电荷在绝缘层表面上积聚而产生电场，进而引起刻蚀性离子的方向在电场作用下发生横向偏转，产生硅横向刻蚀(也称为notching)现象，即，积聚的电荷会增加离子刻蚀绝缘层上方硅通孔两侧的硅材质构成的衬底。这种硅横向刻蚀现象会导致后续硅通孔填充产生空洞，进而会造成漏电流变大等问题，影响硅通孔的电学性能。At present, a through silicon via (TSV), also known as a through silicon via, is a vertical interconnection that penetrates a silicon wafer or chip. TSV can be used to realize 3D integrated circuit packaging, for example, TSV can stack multiple chips to realize chip or circuit interconnection. Preparation of TSVs by dry etching process mainly includes the following steps: silicon etching, TSV insulating layer deposition, TSV insulating layer bottom etching, TSV metal filling (deposition barrier layer, seed layer, electroplating Cu filling), etc. Among them, in the TSV etching process, since there is an insulating layer (the material is usually an inorganic insulating material, such as SiO2, SiN, etc.) at the bottom of the TSV, this insulating layer will cause charge to accumulate on the surface of the insulating layer during the etching process. And an electric field is generated, which in turn causes the direction of the etching ions to be laterally deflected under the action of the electric field, resulting in the phenomenon of silicon lateral etching (also called notching), that is, the accumulated charge will increase the ion etching of the two sides of the TSV above the insulating layer. A substrate made of silicon material on the side. This silicon lateral etching phenomenon will lead to voids in the subsequent TSV filling, which in turn will cause problems such as increased leakage current and affect the electrical performance of the TSV.

因此，为了减小或避免硅通孔的刻蚀过程中硅横向刻蚀，本申请实施例通过在刻蚀硅通孔前，提前在硅通孔底部的绝缘层刻蚀一个开口，使得硅通孔底部的绝缘层提前被刻蚀，暴露出电连接层。进而在通过干法刻蚀硅通孔时，由于开口底部暴露有第一电连接层，且第一电连接层电导率较高，电荷不会大量堆积在开口底部，避免了电荷在开口底部积聚而产生电场，从而大大的减小了横向刻蚀的现象；而且，在干法刻蚀过程中，若少量电荷在电连接层表面堆积，少量电荷刻蚀绝缘材料的难度要大于刻蚀硅材料的难度，因此，会进一步的减小横向刻蚀的现象，不易产生空洞，减小或避免了漏电流变大的问题，保障了半导体装置的电学性能。Therefore, in order to reduce or avoid silicon lateral etching during the etching process of the TSV, the embodiment of the present application etches an opening in the insulating layer at the bottom of the TSV in advance before etching the TSV, so that the TSV The insulating layer at the bottom of the hole is etched in advance, exposing the electrical connection layer. Furthermore, when the through-silicon vias are etched by dry method, since the first electrical connection layer is exposed at the bottom of the opening, and the conductivity of the first electrical connection layer is relatively high, a large amount of charges will not accumulate at the bottom of the opening, which avoids the accumulation of charges at the bottom of the opening. And generate an electric field, thereby greatly reducing the phenomenon of lateral etching; moreover, in the dry etching process, if a small amount of charges accumulate on the surface of the electrical connection layer, the difficulty of etching insulating materials with a small amount of charges is greater than that of etching silicon materials Therefore, the phenomenon of lateral etching will be further reduced, voids will not be easily generated, the problem of increased leakage current will be reduced or avoided, and the electrical performance of the semiconductor device will be guaranteed.

此外，实施本申请实施例提供的半导体装置以及该半导体装置的制备方法，可以应用于各种通过干法刻蚀通孔的过程中，尤其是可以减小或避免在刻蚀通孔时因底部绝缘层产生大量电荷堆积的现象。例如：堆叠的多个芯片需要硅通孔连接时，硅通孔底部的电连接层上还覆盖有绝缘层，本申请实施例可以在底部芯片的绝缘层刻蚀出暴露出电连接层的开口，减小或避免在通过干法刻蚀工艺刻蚀硅通孔时出现的横向刻蚀的现象。又例如：在多个芯片之间需要硅通孔形成电连接时，可以在芯片电连接层周围的绝缘层中形成开口，以便通过该开口制作硅通孔形成电连接。其中，具体的实现方式，可以对应参考下述各个实施例，本申请实施例在此暂不赘述。In addition, the implementation of the semiconductor device provided by the embodiment of the present application and the method for manufacturing the semiconductor device can be applied to various processes of etching through holes by dry method, especially to reduce or avoid the problem caused by the bottom when etching the through holes. The insulating layer produces a large amount of charge accumulation phenomenon. For example: when multiple stacked chips need through-silicon via connection, the electrical connection layer at the bottom of the through-silicon via is also covered with an insulating layer. In this embodiment, an opening that exposes the electrical connection layer can be etched on the insulating layer of the bottom chip. , to reduce or avoid the phenomenon of lateral etching that occurs when the through-silicon vias are etched through a dry etching process. Another example: when a through-silicon via is required to form an electrical connection between multiple chips, an opening may be formed in the insulating layer around the electrical connection layer of the chip, so as to make a through-silicon via through the opening to form an electrical connection. Wherein, for specific implementation manners, reference may be made to each of the following embodiments correspondingly, and the embodiments of the present application will not be repeated here.

其次，本申请实施例提供半导体装置的制作方法，可以减小或避免硅通孔在干法刻蚀中出现横向刻蚀的现象，本申请以制作基于硅通孔的半导体装置为例，示例性的说明本申请实施例提供了一种半导体装置的制作方法。Secondly, the embodiment of the present application provides a method for manufacturing a semiconductor device, which can reduce or avoid the phenomenon of lateral etching of through-silicon vias during dry etching. This application takes the manufacture of semiconductor devices based on through-silicon vias as an example. Description The embodiment of the present application provides a method for manufacturing a semiconductor device.

请参阅图1，图1为本申请实施例提供的半导体装置制作方法的步骤流程图，所述方法包括：Please refer to FIG. 1. FIG. 1 is a flow chart of the steps of the semiconductor device manufacturing method provided by the embodiment of the present application. The method includes:

步骤S1，提供第一芯片。Step S1, providing a first chip.

具体的，提供第一芯片，第一芯片包括依次层叠的第一衬底、第一互连层和第一绝缘层，第一互连层包括第二绝缘层和第一电连接层，所述第一绝缘层为无机绝缘材料。其中，第一互连层中第一电连接层指的是包含导电布线(如：金属布线)和绝缘介质的一层，第一电连接层中的导电布线可以通过硅通孔或者金属通孔与其他层的导电布线(如：其他电连接层)形成电连接。另外，该第一芯片(die)是由晶圆(wafer)切割成的die。请参考附图2，图2是本申请实施例提供的一种第一芯片的截面图。如图2所示，以左右方向为X轴方向，在第一芯片10中，垂直于所述第一衬底101厚度(第一衬底101表面)的方向为X轴方向。沿着X轴方向，即是第一衬底101、第一互连层102和第一绝缘层103的长度方向，所述第一衬底101、第一互连层102和第一绝缘层103的宽度方向为Z轴方向。其中，第一互连层102包括第二绝缘层1021和第一电连接层1022。其中，第一绝缘层为无机绝缘材料，例如SiO2、SiN等。另外，在以下相关实施例的半导体截面图同样适用于图2所示的坐标系(X轴、X轴和Z轴)。Specifically, a first chip is provided, the first chip includes a first substrate, a first interconnection layer and a first insulating layer stacked in sequence, the first interconnection layer includes a second insulating layer and a first electrical connection layer, the The first insulating layer is an inorganic insulating material. Wherein, the first electrical connection layer in the first interconnection layer refers to a layer including conductive wiring (such as: metal wiring) and an insulating medium, and the conductive wiring in the first electrical connection layer can pass through silicon vias or metal vias Form electrical connection with conductive wiring of other layers (such as: other electrical connection layers). In addition, the first die is a die cut from a wafer. Please refer to accompanying drawing 2, which is a cross-sectional view of a first chip provided by an embodiment of the present application. As shown in FIG. 2 , the left-right direction is the X-axis direction, and in the first chip 10 , the direction perpendicular to the thickness of the first substrate 101 (the surface of the first substrate 101 ) is the X-axis direction. Along the X-axis direction, that is, the length direction of the first substrate 101, the first interconnection layer 102 and the first insulating layer 103, the first substrate 101, the first interconnection layer 102 and the first insulating layer 103 The width direction is the Z-axis direction. Wherein, the first interconnection layer 102 includes a second insulating layer 1021 and a first electrical connection layer 1022 . Wherein, the first insulating layer is an inorganic insulating material, such as SiO2, SiN and the like. In addition, the semiconductor cross-sectional views in the following related embodiments are also applicable to the coordinate system (X axis, X axis and Z axis) shown in FIG. 2 .

需要说明的是，可以先提供第一衬底101和第一互连层102，第一互连层102中至少包含第二绝缘层1021和第一电连接层1022。第二绝缘层1021的材质和第一电连接层1022的材质可以根据需求自主选择，其中，第二绝缘层1021材质的导电性要比第一电连接层1022材质的导电性差，例如：第一电连接层1022材质可以是金属或其他导电材料。然后再在第一互连层102表面沉积第一绝缘层103，对第一绝缘层103进行化学机械抛光，使得第一绝缘层103与第一衬底101齐平。另外，第一芯片10中的第一衬底101表面还可以制作有晶体管等有源器件，本申请实施例在此暂不赘述。It should be noted that the first substrate 101 and the first interconnection layer 102 may be provided first, and the first interconnection layer 102 includes at least a second insulating layer 1021 and a first electrical connection layer 1022 . The material of the second insulating layer 1021 and the material of the first electrical connection layer 1022 can be independently selected according to requirements, wherein the conductivity of the material of the second insulating layer 1021 is worse than that of the material of the first electrical connection layer 1022, for example: the first The material of the electrical connection layer 1022 can be metal or other conductive materials. Then, a first insulating layer 103 is deposited on the surface of the first interconnection layer 102 , and chemical mechanical polishing is performed on the first insulating layer 103 so that the first insulating layer 103 is flush with the first substrate 101 . In addition, active devices such as transistors may also be fabricated on the surface of the first substrate 101 in the first chip 10 , which will not be described in this embodiment of the present application.

步骤S2，对第一绝缘层进行刻蚀，在第一绝缘层表面形成暴露出第一电连接层的第一开口。Step S2, etching the first insulating layer to form a first opening exposing the first electrical connection layer on the surface of the first insulating layer.

具体的，对第一绝缘层进行刻蚀，在第一绝缘层表面形成暴露出第一电连接层的第一开口。请参考附图3，图3是本申请实施例提供的一种带有第一开口的第一芯片的截面图。如图3所示，第一绝缘层103表面有暴露出第一电连接层1022的第一开口104，即第一开口104的位置位于第一电连接层1022上方。其中，可以采用刻蚀工艺在第一绝缘层103表面制作绝缘层开口(即，第一开口104)，露出第一电连接层。Specifically, the first insulating layer is etched to form a first opening exposing the first electrical connection layer on the surface of the first insulating layer. Please refer to accompanying drawing 3, which is a cross-sectional view of a first chip with a first opening provided by an embodiment of the present application. As shown in FIG. 3 , the surface of the first insulating layer 103 has a first opening 104 exposing the first electrical connection layer 1022 , that is, the position of the first opening 104 is above the first electrical connection layer 1022 . Wherein, an insulating layer opening (ie, the first opening 104 ) may be formed on the surface of the first insulating layer 103 by an etching process to expose the first electrical connection layer.

可选的，在垂直于所述第一衬底的方向上，所述第一绝缘层厚度大于0微米小于或等于2微米。相较于现有技术中第一绝缘层的厚度，可以在垂直于所述第一衬底的方向上，增加第一绝缘层的厚度至2微米。例如，第一绝缘层厚度在1微米到2微米之间有第一开口的情况下，比目前第一绝缘层厚度在0-1微米之间有第一开口的情况下，电荷在第一开口底部堆积的程度大大减小。而且由于随着第一绝缘层厚度的增加，在刻蚀过程中电荷堆积的概率也随之减小，进而可以进一步的减小电荷堆积所产生的电场对刻蚀性离子方向的影响，从而减小或避免横向刻蚀现象。Optionally, in a direction perpendicular to the first substrate, the thickness of the first insulating layer is greater than 0 microns and less than or equal to 2 microns. Compared with the thickness of the first insulating layer in the prior art, the thickness of the first insulating layer can be increased to 2 microns in the direction perpendicular to the first substrate. For example, when the thickness of the first insulating layer has a first opening between 1 micron and 2 microns, compared with the case where the thickness of the first insulating layer has a first opening between 0-1 micron at present, the electric charge is in the first opening. The degree of bottom build-up is greatly reduced. Moreover, as the thickness of the first insulating layer increases, the probability of charge accumulation in the etching process also decreases, which can further reduce the influence of the electric field generated by charge accumulation on the direction of etching ions, thereby reducing the Minimize or avoid lateral etching phenomenon.

需要说明的是，在刻蚀第一开口104时，因为第一开口104位于第一绝缘层103中，所 以，为了保证第一开口104底部充分暴露，即使刻蚀过程中电荷在绝缘层中积聚，该积聚的电荷也不会出现横向刻蚀绝缘层的现象。It should be noted that, when etching the first opening 104, since the first opening 104 is located in the first insulating layer 103, in order to ensure that the bottom of the first opening 104 is fully exposed, even if charges accumulate in the insulating layer during the etching process , the accumulated charge will not etch the insulating layer laterally.

还需要说明的是，在刻蚀第一开口104时可以采用干法刻蚀工艺刻蚀该开口，本申请实施例对刻蚀方法并不做具体的限制。It should also be noted that, when etching the first opening 104, the opening may be etched by a dry etching process, and the embodiment of the present application does not specifically limit the etching method.

还需要说明的是，本申请实施例对第一开口104的形状暂不限制。例如：在垂直于第一衬底101的方向上，该第一开口104的形状可以是规则的圆形、椭圆形或多边形等等。It should also be noted that the embodiment of the present application does not limit the shape of the first opening 104 temporarily. For example: in a direction perpendicular to the first substrate 101 , the shape of the first opening 104 may be a regular circle, ellipse, or polygon.

步骤S3，提供第二芯片。Step S3, providing a second chip.

具体的，提供第二芯片，该第二芯片包括依次层叠的第二衬底、第二互连层和第三绝缘层，第二互连层包括第四绝缘层和第二电连接层。其中，第二互连层中第二电连接层指的也是包含导电布线(如：金属布线)和绝缘介质的一层，第二电连接层中的导电布线可以通过硅通孔或者金属通孔与其他层的导电布线(如：其他电连接层)形成电连接。请参考附图4，图4是本申请实施例提供的一种第二芯片的截面图。如图4所示，第二芯片20包括依次层叠的第二衬底201、第二互连层202和第三绝缘层203，第二互连层202包括第四绝缘层2021和第二电连接层2022。Specifically, a second chip is provided, and the second chip includes a second substrate, a second interconnection layer, and a third insulating layer stacked in sequence, and the second interconnection layer includes a fourth insulating layer and a second electrical connection layer. Wherein, the second electrical connection layer in the second interconnection layer refers to a layer that also includes conductive wiring (such as: metal wiring) and an insulating medium, and the conductive wiring in the second electrical connection layer can pass through silicon vias or metal vias Form electrical connection with conductive wiring of other layers (such as: other electrical connection layers). Please refer to accompanying drawing 4, which is a cross-sectional view of a second chip provided by an embodiment of the present application. As shown in FIG. 4, the second chip 20 includes a second substrate 201, a second interconnection layer 202, and a third insulating layer 203 stacked in sequence, and the second interconnection layer 202 includes a fourth insulating layer 2021 and a second electrical connection. Layer 2022.

需要说明的是，提供第二芯片20的相关步骤，还可以对应参考上述步骤S1中提供第一芯片10的相关描述，本申请实施例在此暂不赘述。It should be noted that, for the relevant steps of providing the second chip 20 , reference may also be made to the relevant description of providing the first chip 10 in the above step S1 , which will not be repeated in this embodiment of the present application.

还需要说明的是，第二芯片20中的第二电连接层2022在第四绝缘层2021中的相对位置可以与第一芯片10中的第一电连接层1022在第二绝缘层2021中的相对位置不同；第二芯片20中的第二电连接层2022的尺寸也可以与第一芯片10中的第一电连接层1022的尺寸不同。It should also be noted that the relative position of the second electrical connection layer 2022 in the second chip 20 in the fourth insulating layer 2021 may be the same as that of the first electrical connection layer 1022 in the first chip 10 in the second insulating layer 2021. The relative positions are different; the size of the second electrical connection layer 2022 in the second chip 20 may also be different from the size of the first electrical connection layer 1022 in the first chip 10 .

还需要说明的是，第二芯片20的第二衬底201、第二互连层202和第三绝缘层203与第一芯片10的第一衬底101、第一互连层102和第一绝缘层103之间对应的材质可以相同也可以不同，本申请实施例对此不作具体的限定。其中，第二衬底201表面也可以制作有晶体管等有源器件，本申请实施例在此暂不赘述。It should also be noted that the second substrate 201 , the second interconnection layer 202 and the third insulating layer 203 of the second chip 20 are different from the first substrate 101 , the first interconnection layer 102 and the first The corresponding materials of the insulating layers 103 may be the same or different, which is not specifically limited in this embodiment of the present application. Wherein, active devices such as transistors may also be fabricated on the surface of the second substrate 201 , which will not be described here in the embodiment of the present application.

可选的，所述提供第二芯片，步骤之后还包括：以所述第二衬底背面向上的方式，将所述第二芯片临时键合至支撑基板，并对所述第二衬底背面进行减薄。请参考附图5，图5是本申请实施例提供的一种带有支撑基板的第二芯片的截面图。如图5所示，为了方便减薄第二衬底201，可以先将第二芯片20临时键合至支撑基板204，而且减薄第二衬底的厚度可以提高硅通孔的电学性能以及减小半导体装置的体积。另外，该方式可以便于将第二芯片20的第二衬底201背面与第一绝缘层进行直接键合。Optionally, after the step of providing the second chip, the step further includes: temporarily bonding the second chip to the supporting substrate with the back side of the second substrate facing up, and bonding the back side of the second substrate Thinning is performed. Please refer to FIG. 5 , which is a cross-sectional view of a second chip with a supporting substrate provided in an embodiment of the present application. As shown in FIG. 5 , in order to facilitate the thinning of the second substrate 201, the second chip 20 can be temporarily bonded to the supporting substrate 204 first, and thinning the thickness of the second substrate can improve the electrical performance of the TSV and reduce the thickness of the second substrate. The volume of the small semiconductor device. In addition, this way can facilitate the direct bonding of the back surface of the second substrate 201 of the second chip 20 and the first insulating layer.

可选的，在垂直于所述第二衬底方向上，所述第二衬底的厚度大于或等于5微米且小于或等于100微米。由于第二衬底中还可能制作有晶体管等有源器件，所以可以根据业务需求，第二衬底的厚度在5μm-100μm之间。另外，如图5所示，减薄第二衬底201的厚度可以提高硅通孔的电学性能(缩短硅通孔的长度以提高电学性能)以及减小半导体装置的体积。Optionally, in a direction perpendicular to the second substrate, the thickness of the second substrate is greater than or equal to 5 microns and less than or equal to 100 microns. Since active devices such as transistors may also be fabricated in the second substrate, the thickness of the second substrate may be between 5 μm and 100 μm according to business requirements. In addition, as shown in FIG. 5 , reducing the thickness of the second substrate 201 can improve the electrical performance of the TSV (shorten the length of the TSV to improve the electrical performance) and reduce the volume of the semiconductor device.

步骤S4，将第一芯片与第二芯片键合。Step S4, bonding the first chip and the second chip.

具体的，将第一芯片与第二芯片键合其中，第二芯片以背对的方式层叠在第一芯片上；请参考附图6，图6是本申请实施例提供的一种键合后的第一芯片和第二芯片的截面图。如图6所示，将如图3所示第一芯片10与如图4所示第二芯片20直接键合连接，其中，该第二芯片20的第二衬底201的背面与第一芯片10的第一绝缘层103连接。Specifically, the first chip and the second chip are bonded, and the second chip is laminated on the first chip in a back-to-back manner; please refer to the accompanying drawing 6, which is a bonded Cross-sectional views of the first chip and the second chip. As shown in FIG. 6, the first chip 10 shown in FIG. 3 is directly bonded to the second chip 20 shown in FIG. The first insulating layer 103 of 10 is connected.

可选的，所述将所述第一芯片与所述第二芯片键合的步骤，包括：通过所述支撑基板，向所述第一衬底正面方向，将所述第二芯片的所述第二衬底背面与所述第一芯片的所述第一绝缘层进行直接键合；去除所述支撑基板。在第二芯片20临时键合至支撑基板204时，通过 支撑基板204，将所述第二芯片的所述第二衬底背面与所述第一芯片的所述第一绝缘层进行直接键合；并在键合后去除所述支撑基板204。Optionally, the step of bonding the first chip to the second chip includes: bonding the second chip to the front of the first substrate through the support substrate. The back side of the second substrate is directly bonded to the first insulating layer of the first chip; and the supporting substrate is removed. When the second chip 20 is temporarily bonded to the supporting substrate 204, the back surface of the second substrate of the second chip is directly bonded to the first insulating layer of the first chip through the supporting substrate 204 ; and remove the support substrate 204 after bonding.

步骤S5，在第一绝缘层的第一开口对应的位置，对键合后的第二芯片进行刻蚀，在第二芯片表面形成暴露出第一开口的第三开口。Step S5 , etching the bonded second chip at the position corresponding to the first opening of the first insulating layer, and forming a third opening exposing the first opening on the surface of the second chip.

具体的，在第一绝缘层的第一开口对应的位置，对键合后的第二芯片进行刻蚀，在第二芯片表面形成暴露出第一开口的第三开口，其中，第一开口的开口区域在第三开口的开口区域中。请参考附图7，图7是本申请实施例提供的一组带有第三开口的半导体装置的截面图。如图7中(1)所示，对第二芯片20，在第一绝缘层103的第一开口104对应的位置进行刻蚀，在第三绝缘层203表面形成第三开口205，该第三开口205完全暴露出第一开口104，即，第一开口104的范围要在第三开口205的范围之内。如图7中(2)所示，在一种可能的实现方式中，为了便于工艺的实现以及半导体的性能，在刻蚀第三开口205时，可以继续对第一绝缘层103进行刻蚀，以完全暴露出第一开口104，以及该第一开口104底部的第一电连接层。Specifically, at the position corresponding to the first opening of the first insulating layer, the bonded second chip is etched, and a third opening exposing the first opening is formed on the surface of the second chip, wherein the first opening The opening area is in the opening area of the third opening. Please refer to FIG. 7 . FIG. 7 is a cross-sectional view of a group of semiconductor devices with a third opening provided by an embodiment of the present application. As shown in (1) in FIG. 7, the second chip 20 is etched at the position corresponding to the first opening 104 of the first insulating layer 103, and a third opening 205 is formed on the surface of the third insulating layer 203. The third The opening 205 completely exposes the first opening 104 , that is, the range of the first opening 104 should be within the range of the third opening 205 . As shown in (2) in FIG. 7 , in a possible implementation, in order to facilitate the realization of the process and the performance of the semiconductor, when the third opening 205 is etched, the first insulating layer 103 can be etched continuously, In order to completely expose the first opening 104 and the first electrical connection layer at the bottom of the first opening 104 .

需要说明的是，为了保证后续形成硅通孔时，该硅通孔不存在空隙，该第一开口104的顶部开口区域在第三开口205的底部开口区域中，例如：第三开口205的底部形状可以与第一开口104的顶部形状保持一致。It should be noted that, in order to ensure that there is no gap in the TSV when the TSV is subsequently formed, the top opening area of the first opening 104 is in the bottom opening area of the third opening 205 , for example: the bottom of the third opening 205 The shape may be consistent with the shape of the top of the first opening 104 .

可选的，所述第一开口暴露出部分所述第一电连接层；所述第二开口暴露出部分所述第三电连接层。Optionally, the first opening exposes part of the first electrical connection layer; the second opening exposes part of the third electrical connection layer.

步骤S6，在第一开口处和第三开口处形成硅通孔。Step S6, forming TSVs at the first opening and the third opening.

具体的，在第一开口处和第三开口处形成硅通孔。请参考附图8至图10，图8和图9是本申请实施例提供的一组带有硅通孔绝缘层的半导体装置的截面图，图10是本申请实施例提供的一种带有硅通孔的半导体装置的截面图。如图8所示，在硅通孔(即，第一开口104和第三开口205)内制作硅通孔绝缘层206；如图9所示，将第一开口104底部的硅通孔绝缘层206刻蚀，露出第一电连接层1022。如图10所示，在第一开口104和第三开口205形成的硅通孔内进行导电材料填充(如：金属材料填充)形成硅通孔207，其中，填充工艺可以采用物理气相沉积、电镀、化学镀等方法对硅通孔进行填充。另外，还可以结合化学机械抛光工艺去除在填充硅通孔过程中沉积在第三绝缘层203表面的导电材料。另外，还可以结合化学机械抛光工艺使得硅通孔207的表面与第三绝缘层203的表面齐平。Specifically, through silicon vias are formed at the first opening and the third opening. Please refer to accompanying drawings 8 to 10, Figures 8 and 9 are cross-sectional views of a group of semiconductor devices with through-silicon via insulating layers provided by embodiments of the present application, and Figure 10 is a set of semiconductor devices with insulating layers provided by embodiments of the present application. A cross-sectional view of a semiconductor device with a through-silicon via. As shown in FIG. 8 , a TSV insulating layer 206 is formed in the TSV (that is, the first opening 104 and the third opening 205 ); as shown in FIG. 9 , the TSV insulating layer at the bottom of the first opening 104 is 206 to expose the first electrical connection layer 1022 . As shown in FIG. 10 , the through-silicon vias formed by the first opening 104 and the third opening 205 are filled with conductive materials (such as filling with metal materials) to form the through-silicon vias 207, wherein the filling process can use physical vapor deposition, electroplating, etc. , electroless plating and other methods to fill the through-silicon vias. In addition, the conductive material deposited on the surface of the third insulating layer 203 during the process of filling the TSVs can also be removed in combination with a chemical mechanical polishing process. In addition, a chemical mechanical polishing process can also be combined to make the surface of the TSV 207 flush with the surface of the third insulating layer 203 .

可选的，所述硅通孔包括相连的第一段硅通孔和第二段硅通孔；所述第一段硅通孔为所述第一开口处形成的硅通孔，所述第一段硅通孔的底部为所述第一电连接层；所述第二段硅通孔为所述第三开口处形成的硅通孔，贯穿所述第二芯片，所述第二段硅通孔的底部连接所述第一段硅通孔，顶部连接所述第三电连接层。如图10所示，硅通孔207包括相连的第一段硅通孔(即，第一开口104处形成的硅通孔、直径较小的一段)和第二段硅通孔(即，第三开口205处形成的硅通孔、直径较大的一段)。需要说明的是，该两个相连的硅通孔相当于一个结构的两个部分，可以一起被制作的。还需要说明的是，此处的直径指的是，在同一竖直横截面中，在第二段硅通孔与第一段硅通孔连接处，所述第一段硅通孔的直径总是小于所述第二段硅通孔的直径。Optionally, the through-silicon via includes a first section of through-silicon via and a second section of through-silicon via; the first section of through-silicon via is a through-silicon via formed at the first opening, and the first section of through-silicon via The bottom of a section of through-silicon via is the first electrical connection layer; the second section of through-silicon via is a through-silicon via formed at the third opening, which runs through the second chip. The bottom of the through hole is connected to the first section of TSV, and the top is connected to the third electrical connection layer. As shown in FIG. 10 , the TSV 207 includes a connected first section of the TSV (that is, the TSV formed at the first opening 104 and a section with a smaller diameter) and a second section of the TSV (that is, the first section of the TSV). The through-silicon hole formed at the third opening 205, a section with a larger diameter). It should be noted that the two connected TSVs are equivalent to two parts of a structure and can be fabricated together. It should also be noted that the diameter here refers to the total diameter of the first section of TSV at the junction of the second section of TSV and the first section of TSV in the same vertical cross section. is smaller than the diameter of the second section of TSVs.

可选的，所述第二段硅通孔在所述第一衬底上的投影覆盖所述第一段硅通孔在所述第一衬底上的投影。需要说明的是，该投影分别指的是在第二段硅通孔和第一段硅通孔上各自连接处区域在第一衬底上的投影，即，第二段硅通孔与第一段硅通孔连接处对应第二段硅通孔连接面的在所述第一衬底上的投影；第一段硅通孔与第二段硅通孔连接处对应第一段硅通孔 连接面的在所述第一衬底上的投影。例如：如上述图7中(2)所示，第二段硅通孔(即，第三开口205处形成的、截面图为矩形的硅通孔)与第一段硅通孔(即，第一开口104处形成的硅通孔、截面图为梯形的硅通孔)连接处中对应第二段硅通孔连接面的在所述第一衬底上的投影、覆盖了所述第一段硅通孔与第二段硅通孔的连接处中对应第一段硅通孔连接面的在所述第一衬底上的投影。Optionally, the projection of the second section of TSVs on the first substrate covers the projection of the first section of TSVs on the first substrate. It should be noted that the projections respectively refer to the projections of the connection areas of the second TSV and the first TSV on the first substrate, that is, the second TSV and the first TSV The connection of the TSV segment corresponds to the projection of the connection surface of the TSV segment of the second segment on the first substrate; the connection of the TSV segment of the first segment and the TSV segment of the second segment corresponds to the connection of the TSV segment of the first segment The projection of the surface on the first substrate. For example: as shown in (2) in FIG. 7 above, the second TSV (that is, the TSV formed at the third opening 205 with a rectangular cross-sectional view) is the same as the first TSV (that is, the first TSV). A TSV formed at an opening 104 (a TSV with a trapezoidal cross-section in the cross-sectional view) corresponds to the projection on the first substrate of the connecting surface of the second section of the TSV, covering the first section The connection between the TSV and the second TSV corresponds to the projection of the connecting surface of the first TSV on the first substrate.

可选的，所述第一段硅通孔的第一端连接所述第二段硅通孔的第二端，且第二端所在的区域覆盖第一端所在的区域。其中，所述第一端为所述第一段硅通孔的且远离第一电连接层的一端，所述第二端为第二段硅通孔的且靠近所述第一绝缘层的一端。在本申请实施例中，第二端所在的区域覆盖第一端所在的区域，即，所述第一段硅通孔要小于第二段硅通孔，以便在后续第一段硅通孔和第二段硅通孔填充时，不易产生空洞，避免了漏电流变大的问题，保障了半导体装置的性能。Optionally, the first end of the first section of TSVs is connected to the second end of the second section of TSVs, and the area where the second end is located covers the area where the first end is located. Wherein, the first end is an end of the first section of TSV and away from the first electrical connection layer, and the second end is an end of the second section of TSV close to the first insulating layer . In the embodiment of the present application, the area where the second end is located covers the area where the first end is located, that is, the first section of TSVs is smaller than the second section of TSVs, so that the subsequent first section of TSVs and TSVs When the second TSV is filled, it is not easy to generate voids, which avoids the problem of increased leakage current and ensures the performance of the semiconductor device.

步骤S7，对第三绝缘层进行刻蚀并填充第一导电材料，形成第一金属通孔。In step S7, the third insulating layer is etched and filled with the first conductive material to form a first metal via.

具体的，对第三绝缘层进行刻蚀并填充第一导电材料，形成第一金属通孔。第一金属通孔的底部连接第二电连接层，顶部连接第三电连接层。其中，与硅通孔在芯片与芯片之间形成电连接不同，金属通孔一般是为了穿过绝缘层在层与层之间形成电连接，例如：金属通孔可以使相邻或间隔的两层，穿过覆盖在电连接层上的绝缘材料形成电连接。而且，一般在形成金属通孔时，是在绝缘层刻蚀通孔后直接填充导电材料，而且通孔底部一般暴露有电连接层，所以金属通孔一般不会出现横向刻蚀的现象。请参考附图11，图11是本申请实施例提供的一种带有第一金属通孔的半导体装置的截面图。如图11所示，对第三绝缘层203进行刻蚀，在第三绝缘层203的表面形成暴露出第二电连接层2022的开口，并该开口处填充第一导电材料，形成第一金属通孔208。需要说明的是，该第一导电材料可以是导电性能好的金属。另外，还可以结合化学机械抛光工艺使得第一金属通孔208的表面与第三绝缘层203的表面齐平。Specifically, the third insulating layer is etched and filled with the first conductive material to form the first metal via. The bottom of the first metal via is connected to the second electrical connection layer, and the top is connected to the third electrical connection layer. Among them, different from through-silicon vias that form electrical connections between chips, metal vias are generally used to pass through insulating layers to form electrical connections between layers. For example: metal vias can make two adjacent or spaced layer to form an electrical connection through the insulating material covering the electrical connection layer. Moreover, when forming a metal through hole, the conductive material is directly filled after the insulating layer etches the through hole, and the bottom of the through hole generally exposes an electrical connection layer, so the metal through hole generally does not undergo lateral etching. Please refer to FIG. 11 . FIG. 11 is a cross-sectional view of a semiconductor device with a first metal via provided by an embodiment of the present application. As shown in FIG. 11, the third insulating layer 203 is etched to form an opening exposing the second electrical connection layer 2022 on the surface of the third insulating layer 203, and the opening is filled with a first conductive material to form a first metal Through hole 208 . It should be noted that the first conductive material may be a metal with good electrical conductivity. In addition, a chemical mechanical polishing process can also be combined to make the surface of the first metal via 208 flush with the surface of the third insulating layer 203 .

步骤S8，在键合后的第二芯片远离第一芯片的一侧形成第三互连层。Step S8, forming a third interconnection layer on the side of the bonded second chip away from the first chip.

具体的，在键合后的第二芯片远离第一芯片的一侧形成第三互连层，所述第三互连层包括第五绝缘层和第三电连接层，其中，第五绝缘层中嵌设第三电连接层或者第三电连接层被暴露在第五绝缘层的表面。第一电连接层和第二电连接层通过硅通孔、第一金属通孔和第三电连接层形成电连接。请参考附图12，图12是本申请实施例提供的一种半导体装置的截面图。如图12所示，在键合后的第二芯片20上(即，第三绝缘层203上)制作第三互连层209，第三互连层209包括第五绝缘层2092和第三电连接层2091，其中，第五绝缘层2092嵌设有第三电连接层2091，该第三电连接层2091底部连接硅通孔207和第一金属通孔208。其中，第一电连接层1021和第二电连接层2022通过硅通孔207、第一金属通孔208和第三电连接层2091形成电连接，获得半导体装置。Specifically, a third interconnection layer is formed on the side of the bonded second chip away from the first chip, and the third interconnection layer includes a fifth insulating layer and a third electrical connection layer, wherein the fifth insulating layer The third electrical connection layer is embedded in or exposed on the surface of the fifth insulating layer. The first electrical connection layer and the second electrical connection layer are electrically connected through the silicon through hole, the first metal through hole and the third electrical connection layer. Please refer to FIG. 12 , which is a cross-sectional view of a semiconductor device provided by an embodiment of the present application. As shown in FIG. 12, a third interconnection layer 209 is fabricated on the bonded second chip 20 (that is, on the third insulating layer 203), and the third interconnection layer 209 includes a fifth insulating layer 2092 and a third electrical connection layer 209. The connection layer 2091 , wherein the fifth insulating layer 2092 is embedded with a third electrical connection layer 2091 , and the bottom of the third electrical connection layer 2091 is connected to the through-silicon via 207 and the first through-metal via 208 . Wherein, the first electrical connection layer 1021 and the second electrical connection layer 2022 are electrically connected through the through-silicon via 207 , the first through-metal via 208 and the third electrical connection layer 2091 to obtain a semiconductor device.

需要说明的是，第三电连接层2091与第一电连接层1021和/或第二电连接层2022的材质可以相同也可以不同。It should be noted that the materials of the third electrical connection layer 2091 and the first electrical connection layer 1021 and/or the second electrical connection layer 2022 may be the same or different.

还需要说明的是，本申请实施例中，所述半导体装置的各层(如，绝缘层、电连接层、衬底等)为规则结构，功能层的厚度是均匀设置的，并且可以保证高的工作效率，这种设计符合现有的芯片、电子设备等小型化、轻薄化发展趋势。而当所述这些各个功能层为非均匀的情况下，但各层的电性连接关系(如：第一电连接层和第二电连接层通过硅通孔、第一金属通孔和第三电连接层形成电连接)是不会改变的，只要符合本实施例截取的截面的层结构和配合关系，均可以解决本申请解决的技术问题及实现本申请的技术效果。It should also be noted that in the embodiment of the present application, each layer of the semiconductor device (such as an insulating layer, an electrical connection layer, a substrate, etc.) has a regular structure, and the thickness of the functional layer is uniformly set, and can ensure high This design conforms to the current trend of miniaturization and thinning of chips and electronic equipment. And when these various functional layers are non-uniform, but the electrical connection relationship of each layer (such as: the first electrical connection layer and the second electrical connection layer through silicon vias, the first metal vias and the third The electrical connection layer to form an electrical connection) will not change, as long as it conforms to the layer structure and coordination relationship of the cross-section intercepted in this embodiment, the technical problems solved in this application can be solved and the technical effects of this application can be realized.

目前，在刻蚀硅通孔底部绝缘层过程中，即第一开口的刻蚀过程中为了将底部电连接层充分露出，通常会进行过刻蚀(over etch)步骤。当底部电连接层为铜Cu时，过刻蚀会导致Cu反溅射到硅通孔侧壁上，对硅通孔侧壁造成Cu污染，会引起硅通孔的击穿电压降低从而对整个硅通孔的电学性能产生负面影响。因此，在第一电连接层的材质为铜的情况下，在所述第一开口处、第一电连接层上方还覆盖有刻蚀停止层，该刻蚀停止层可以在过刻蚀防止铜溅射，保证该硅通孔的性能。At present, in the process of etching the insulating layer at the bottom of the TSV, that is, during the etching process of the first opening, in order to fully expose the bottom electrical connection layer, an over etch step is usually performed. When the bottom electrical connection layer is copper Cu, over-etching will cause Cu back-sputtering to the sidewall of the TSV, causing Cu pollution to the sidewall of the TSV, which will cause the breakdown voltage of the TSV to decrease, thereby affecting the entire TSV. The electrical performance of TSVs is negatively affected. Therefore, when the material of the first electrical connection layer is copper, an etching stop layer is also covered at the first opening and above the first electrical connection layer, and the etching stop layer can prevent copper from being over-etched. Sputtering ensures the performance of the TSVs.

可选的，针对步骤S2，在所述第一电连接层的材质包括铜的情况下，所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，步骤之后还包括：在所述第一绝缘层的所述第一开口内的所述第一电连接层上形成刻蚀停止层，其中，在垂直于所述第一衬底方向上，所述刻蚀停止层厚度小于所述第一开口的深度。Optionally, for step S2, in the case where the material of the first electrical connection layer includes copper, the first insulating layer is etched to form a surface on the surface of the first insulating layer exposing the After the first opening of the first electrical connection layer, the step further includes: forming an etch stop layer on the first electrical connection layer in the first opening of the first insulating layer, wherein, when the first opening is perpendicular to the first insulating layer, In the direction of the first substrate, the thickness of the etching stop layer is smaller than the depth of the first opening.

请参考附图13，图13是本申请实施例提供的一种带有刻蚀停止层的第一芯片的截面图。如图13所示，在第一开口104底部还形成有刻蚀停止层105，为了保证半导体装置的电学性能，该刻蚀停止层105在垂直于第一衬底101方向上(Y轴方向上)厚度小于第一开口104的深度。其中，该刻蚀停止层105采用的工艺可以是选择性沉积工艺，例如化学镀；也可以采用物理气相沉积和刻蚀的方法，本申请实施例在此不再赘述。Please refer to FIG. 13 , which is a cross-sectional view of a first chip with an etch stop layer provided by an embodiment of the present application. As shown in FIG. 13, an etch stop layer 105 is also formed at the bottom of the first opening 104. In order to ensure the electrical performance of the semiconductor device, the etch stop layer 105 is formed in a direction perpendicular to the first substrate 101 (in the Y-axis direction). ) thickness is less than the depth of the first opening 104. Wherein, the process adopted for the etching stop layer 105 may be a selective deposition process, such as electroless plating; physical vapor deposition and etching may also be used, which will not be repeated in this embodiment of the present application.

基于图13所示的第一芯片10，当第一开口104底部沉积有刻蚀停止层105时，再与第二芯片20堆叠后，构成半导体装置。请参考附图14和图15A，图14和图15A是本申请实施例提供的一组带有刻蚀停止层的半导体装置的截面图。如图14所示，在基于图13所示的第一芯片10与第二芯片20键合后，第一开口104底部沉积有刻蚀停止层105；如图15A所示，在形成硅通孔207的过程中，该刻蚀停止层105位于该硅通孔207底部。其中，形成硅通孔207的步骤以及后续其他相关步骤，还可以对应参考上述步骤S5-步骤S8的相关描述，本申请实施例在此暂不赘述。Based on the first chip 10 shown in FIG. 13 , when the etching stop layer 105 is deposited on the bottom of the first opening 104 , it is stacked with the second chip 20 to form a semiconductor device. Please refer to FIG. 14 and FIG. 15A , which are cross-sectional views of a set of semiconductor devices with an etch stop layer according to an embodiment of the present application. As shown in FIG. 14, after the first chip 10 and the second chip 20 are bonded based on FIG. 13, an etch stop layer 105 is deposited on the bottom of the first opening 104; 207 , the etch stop layer 105 is located at the bottom of the TSV 207 . Wherein, for the step of forming the TSV 207 and other subsequent related steps, reference may also be made to the relevant descriptions of the above-mentioned step S5-step S8, and the embodiment of the present application will not repeat them here.

可选的，刻蚀停止层的材质为Ni、NiMoP、NiP、NiB、Co、CoWP、Ti、Ta、TiN、TaN、TiW、Al、Cr、W、Mn、Mg中的一种。Optionally, the material of the etching stop layer is one of Ni, NiMoP, NiP, NiB, Co, CoWP, Ti, Ta, TiN, TaN, TiW, Al, Cr, W, Mn, Mg.

可选的，针对步骤S1，所述第一芯片包括依次层叠的第一衬底、第一互连层、刻蚀停止层和第一绝缘层，所述刻蚀停止层嵌于第一绝缘层，底部覆盖部分或全部第一电连接层、顶部连接第一绝缘层。针对步骤S2，所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口步骤，包括：对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出与所述第一电连接层连接的所述刻蚀停止层的第一开口。Optionally, for step S1, the first chip includes a first substrate, a first interconnection layer, an etch stop layer and a first insulating layer stacked in sequence, and the etch stop layer is embedded in the first insulating layer , the bottom covers part or all of the first electrical connection layer, and the top is connected to the first insulating layer. For step S2, the step of etching the first insulating layer and forming a first opening exposing the first electrical connection layer on the surface of the first insulating layer includes: performing etching to form a first opening exposing the etching stop layer connected to the first electrical connection layer on the surface of the first insulating layer.

请参考附图15B，图15B是本申请实施例提供的一组带有刻蚀停止层的半导体的截面图。如图15B中(1)所示，在第一开口104底部暴露出部分刻蚀停止层105，为了保证半导体装置的电学性能，该刻蚀停止层105在第一开口104的区域内完全覆盖了第一电连接层1022。如图15B中(2)所示，刻蚀停止层105嵌于第一绝缘层103，底部覆盖部分或全部第一电连接层1022、顶部连接第一绝缘层103。在形成硅通孔207的过程中，该刻蚀停止层105位于该硅通孔207底部。其中，该刻蚀停止层105可以是在刻蚀第一开口104之前被制作完成的，采用的工艺可以是选择性沉积工艺，例如化学镀；也可以采用物理气相沉积和刻蚀的方法，本申请实施例在此不再赘述。Please refer to FIG. 15B , which is a cross-sectional view of a group of semiconductors with an etch stop layer provided by an embodiment of the present application. As shown in (1) in FIG. 15B , a part of the etch stop layer 105 is exposed at the bottom of the first opening 104. In order to ensure the electrical performance of the semiconductor device, the etch stop layer 105 completely covers the area of the first opening 104. The first electrical connection layer 1022 . As shown in (2) in FIG. 15B , the etching stop layer 105 is embedded in the first insulating layer 103 , the bottom covers part or all of the first electrical connection layer 1022 , and the top is connected to the first insulating layer 103 . During the formation of the TSV 207 , the etch stop layer 105 is located at the bottom of the TSV 207 . Wherein, the etch stop layer 105 can be completed before etching the first opening 104, and the process used can be a selective deposition process, such as chemical plating; physical vapor deposition and etching methods can also be used. The application embodiments will not be repeated here.

需要说明的是，本申请实施例中刻蚀停止层的顶部区域大于或等于第一开口底部区域刻蚀停止层的底部区域小于或等于第一电连接层的顶部区域。It should be noted that in the embodiment of the present application, the top area of the etch stop layer is greater than or equal to the bottom area of the first opening, and the bottom area of the etch stop layer is smaller than or equal to the top area of the first electrical connection layer.

还需要说明的是，形成硅通孔207的步骤以及后续其他相关步骤，还可以对应参考上述 步骤S5-步骤S8的相关描述，本申请实施例在此暂不赘述。It should also be noted that for the step of forming TSV 207 and other subsequent related steps, reference may also be made to the relevant descriptions of the above steps S5-Step S8, which will not be repeated here in this embodiment of the present application.

进一步的，在键合第一芯片和第二芯片时，采用非晶硅键合层等实现直接键合，可降低键合工艺温度。因此，本申请实施例可以通过如：非晶硅键合层、绝缘键合层等方式键合连接第一芯片和第二芯片。Further, when bonding the first chip and the second chip, an amorphous silicon bonding layer is used to realize direct bonding, which can reduce the temperature of the bonding process. Therefore, in the embodiment of the present application, the first chip and the second chip can be bonded and connected by methods such as an amorphous silicon bonding layer, an insulating bonding layer, and the like.

下面以键合层为非晶硅键合层的情况为例，简单介绍下，存在键合层时的半导体装置的几种制作方法：Taking the case where the bonding layer is an amorphous silicon bonding layer as an example, briefly introduce several manufacturing methods of semiconductor devices when there is a bonding layer:

方式一：在制作第一开口前制作键合层。Method 1: making a bonding layer before making the first opening.

可选的，所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，步骤之前还包括：在所述第一绝缘层表面上沉积覆盖非晶硅键合层；所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口的步骤，包括：对所述第一绝缘层和所述非晶硅键合层进行刻蚀，在所述非晶硅键合层表面形成暴露出所述第一电连接层的所述第一开口。Optionally, before the step of etching the first insulating layer and forming a first opening exposing the first electrical connection layer on the surface of the first insulating layer, the step further includes: depositing an amorphous silicon bonding layer on the surface of the insulating layer; the step of etching the first insulating layer and forming a first opening exposing the first electrical connection layer on the surface of the first insulating layer , comprising: etching the first insulating layer and the amorphous silicon bonding layer, and forming the first opening exposing the first electrical connection layer on the surface of the amorphous silicon bonding layer.

请参考附图16至附图18，图16和图17是本申请实施例提供的一组带有键合层106的第一芯片的截面图；图18是本申请实施例提供的一种基于图17所示第一芯片的半导体装置的截面图。其中，Please refer to accompanying drawings 16 to 18, Fig. 16 and Fig. 17 are cross-sectional views of a group of first chips with a bonding layer 106 provided by the embodiment of the present application; FIG. 17 is a cross-sectional view of the semiconductor device of the first chip. in,

如图16所示，针对步骤S1，在提供第一芯片10时，在所述第一绝缘层103表面形成暴露出所述第一电连接层1022的第一开口104之前，在所述第一绝缘层103表面上沉积覆盖非晶硅键合层106。其中，可以根据需要控制非晶硅键合层106的厚度，还可以结合化学机械抛光工艺使得非晶硅键合层106的表面与第一绝缘层103的表面齐平。As shown in FIG. 16, for step S1, when providing the first chip 10, before forming the first opening 104 exposing the first electrical connection layer 1022 on the surface of the first insulating layer 103, the first An amorphous silicon bonding layer 106 is deposited on the surface of the insulating layer 103 . Wherein, the thickness of the amorphous silicon bonding layer 106 can be controlled as required, and a chemical mechanical polishing process can also be combined to make the surface of the amorphous silicon bonding layer 106 flush with the surface of the first insulating layer 103 .

如图17所示，针对步骤S2，本申请实施例可以对第一绝缘层103和非晶硅键合层106进行刻蚀，在所述非晶硅键合层106表面形成暴露出所述第一电连接层1022的所述第一开口104，其中，相较于图3所示的第一芯片10，在Y轴方向上，该图17所示的第一芯片10中的第一开口104的深度为第一绝缘层103和非晶硅键合层106的厚度之和。另外，该刻蚀第一开口104时，可以通过干法刻蚀。As shown in FIG. 17 , for step S2, the embodiment of the present application can etch the first insulating layer 103 and the amorphous silicon bonding layer 106, forming a layer on the surface of the amorphous silicon bonding layer 106 that exposes the first insulating layer 103. The first opening 104 of an electrical connection layer 1022, wherein, compared with the first chip 10 shown in FIG. 3 , in the Y-axis direction, the first opening 104 in the first chip 10 shown in FIG. 17 The depth is the sum of the thicknesses of the first insulating layer 103 and the amorphous silicon bonding layer 106 . In addition, when etching the first opening 104, dry etching may be used.

如图18所示，针对步骤S3，将第一芯片10和第二芯片20键合，非晶硅键合层106键合可以连接第一芯片10和第二芯片20。As shown in FIG. 18 , for step S3 , the first chip 10 and the second chip 20 are bonded, and the bonding of the amorphous silicon bonding layer 106 can connect the first chip 10 and the second chip 20 .

需要说明的是，后续有关制作硅通孔形成电连接以及其他相关方面的相关描述，还可以对应参考上述实施例步骤S4-步骤S8的相关描述，本申请实施例暂不赘述。It should be noted that, for subsequent descriptions related to fabricating through-silicon vias to form electrical connections and other related aspects, reference may also be made to the relevant descriptions of step S4-step S8 in the above embodiment, which will not be repeated in the embodiment of the present application.

方式二：在制作第一开口后制作键合层，且键合层的厚度小于预设阈值。Manner 2: making a bonding layer after making the first opening, and the thickness of the bonding layer is less than a preset threshold.

可选的，对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，步骤之后还包括：在所述第一绝缘层表面上沉积覆盖非晶硅键合层；在垂直于所述第一衬底方向上，所述非晶硅键合层的厚度小于预设阈值(如预设阈值可以是所述第一开口的深度)时，将第一芯片和第二芯片直接键合，或者，将第一绝缘层表面沉积的非晶硅键合层进行抛光直至所述非晶硅键合层的表面与所述第一衬底表面平齐。Optionally, etching the first insulating layer to form a first opening exposing the first electrical connection layer on the surface of the first insulating layer, after the step, further includes: A bonding layer of amorphous silicon is deposited on the surface; in a direction perpendicular to the first substrate, the thickness of the bonding layer of amorphous silicon is less than a preset threshold (for example, the preset threshold may be the thickness of the first opening depth), the first chip and the second chip are directly bonded, or the amorphous silicon bonding layer deposited on the surface of the first insulating layer is polished until the surface of the amorphous silicon bonding layer and the first The substrate surface is even.

请参考附图19和附图20，图19是本申请实施例提供的一种基于图3的带有键合层的第一芯片截面图；图20是本申请实施例提供的一种基于图19所示第一芯片的半导体装置的截面图。其中，Please refer to accompanying drawings 19 and 20. Fig. 19 is a sectional view of a first chip with a bonding layer based on Fig. 3 provided by an embodiment of the present application; 19 is a cross-sectional view of the semiconductor device of the first chip. in,

如图19所示，针对步骤S2，对第一绝缘层103进行刻蚀，在所述第一绝缘层103表面形成暴露出所述第一电连接层1022的所述第一开口104之后，再在第一绝缘层103表面上沉 积覆盖非晶硅键合层106。由于第一绝缘层103中存在第一开口104，所以在制作非晶硅键合层106时，非晶硅键合层106会覆盖第一开口104底部和两侧。As shown in FIG. 19, for step S2, the first insulating layer 103 is etched, and after the first opening 104 exposing the first electrical connection layer 1022 is formed on the surface of the first insulating layer 103, then A bonding layer 106 covering amorphous silicon is deposited on the surface of the first insulating layer 103 . Since the first opening 104 exists in the first insulating layer 103 , when the amorphous silicon bonding layer 106 is formed, the amorphous silicon bonding layer 106 will cover the bottom and both sides of the first opening 104 .

在键合层的厚度小于预设阈值(如：第一开口104的深度)的情况下，例如：在非晶硅键合层106沉积的厚度不足以填平第一开口104的情况下。如图20所示，针对步骤S3，将第一芯片10和第二芯片20键合，非晶硅键合层106键合可以位于第一芯片10和第二芯片20之间，键合第一芯片10和第二芯片20，并获得如图20所示的半导体装置。In the case that the thickness of the bonding layer is less than a predetermined threshold (eg, the depth of the first opening 104 ), for example, the deposited thickness of the amorphous silicon bonding layer 106 is not enough to fill up the first opening 104 . As shown in FIG. 20, for step S3, the first chip 10 and the second chip 20 are bonded, and the bonding of the amorphous silicon bonding layer 106 can be located between the first chip 10 and the second chip 20, and the first chip 10 and the second chip 20 are bonded. chip 10 and the second chip 20, and a semiconductor device as shown in FIG. 20 is obtained.

其中，所述在所述第一绝缘层的所述第一开口对应的位置，对键合后的所述第二芯片进行刻蚀，在所述第二芯片表面形成暴露出所述第一开口的第三开口，步骤之后还包括：在所述第一绝缘层的所述第一开口对应的位置，对所述非晶硅键合层进行刻蚀，暴露出所述第一电连接层。沉积非晶硅键合层后，还需要刻蚀第一开口底部的非晶硅键合层，以便暴露出开口底部连接的第一电连接层，以形成电连接。Wherein, at the position corresponding to the first opening of the first insulating layer, the bonded second chip is etched, and the first opening is exposed on the surface of the second chip. After the step, the step further includes: etching the amorphous silicon bonding layer at a position corresponding to the first opening of the first insulating layer to expose the first electrical connection layer. After the amorphous silicon bonding layer is deposited, the amorphous silicon bonding layer at the bottom of the first opening needs to be etched to expose the first electrical connection layer connected to the bottom of the opening to form an electrical connection.

即，针对步骤S5，在刻蚀第三开口205之后，可以将第一开口104内(例如：底部和两侧)的非晶硅键合层106刻蚀掉，以暴露出第一开口104底部的第一电连接层1022。That is, for step S5, after etching the third opening 205, the amorphous silicon bonding layer 106 in the first opening 104 (for example: the bottom and both sides) can be etched away, so as to expose the bottom of the first opening 104 The first electrical connection layer 1022.

需要说明的是，后续有关制作硅通孔形成电连接以及其他相关方面的相关描述，还可以对应参考上述实施例步骤S4-步骤S8的相关描述，本申请实施例暂不赘述。It should be noted that, for subsequent descriptions related to fabricating through-silicon vias to form electrical connections and other related aspects, reference may also be made to the relevant descriptions of step S4-step S8 in the above embodiment, which will not be repeated in the embodiment of the present application.

方式三：在制作第一开口后制作键合层，且键合层的厚度大于预设阈值。Manner 3: making a bonding layer after making the first opening, and the thickness of the bonding layer is greater than a preset threshold.

可选的，对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，步骤之后还包括：在所述第一绝缘层表面上沉积覆盖非晶硅键合层；在垂直于所述第一衬底方向(Y轴方向)上，所述非晶硅键合层的厚度大于所述第一开口的深度时，对所述非晶硅键合层进行抛光直至所述非晶硅键合层的表面与所述第一衬底表面平齐。Optionally, etching the first insulating layer to form a first opening exposing the first electrical connection layer on the surface of the first insulating layer, after the step, further includes: A bonding layer of amorphous silicon is deposited on the surface; in a direction perpendicular to the first substrate (Y-axis direction), when the thickness of the bonding layer of amorphous silicon is greater than the depth of the first opening, the The amorphous silicon bonding layer is polished until the surface of the amorphous silicon bonding layer is flush with the surface of the first substrate.

请参考附图21和附图22，图21是本申请实施例提供的另一种基于图3的带有键合层的第一芯片截面图；图22是本申请实施例提供的一种基于图21所示第一芯片的半导体装置的截面图。其中，Please refer to accompanying drawings 21 and 22. Fig. 21 is another cross-sectional view of the first chip with a bonding layer based on Fig. 3 provided by the embodiment of the present application; FIG. 21 is a cross-sectional view of the semiconductor device of the first chip. in,

如图21所示，针对步骤S2，对第一绝缘层103进行刻蚀，在所述第一绝缘层103表面形成暴露出所述第一电连接层1022的所述第一开口104之后，再在第一绝缘层103表面上沉积覆盖非晶硅键合层106。由于第一绝缘层103中存在第一开口104，所以在制作非晶硅键合层106时，非晶硅键合层106会覆盖第一开口104底部和两侧。As shown in FIG. 21, for step S2, the first insulating layer 103 is etched, and after the first opening 104 exposing the first electrical connection layer 1022 is formed on the surface of the first insulating layer 103, then A bonding layer 106 covering amorphous silicon is deposited on the surface of the first insulating layer 103 . Since the first opening 104 exists in the first insulating layer 103 , when the amorphous silicon bonding layer 106 is formed, the amorphous silicon bonding layer 106 will cover the bottom and both sides of the first opening 104 .

在键合层的厚度大于预设阈值(如：第一开口104的深度)的情况下，例如：在非晶硅键合层106沉积的厚度足以填平第一开口104的情况下。如图21所示，针对步骤S3，可以先将沉积的非晶硅键合层106进行抛光直至所述非晶硅键合层的表面与所述第一衬底表面平齐后，将第一芯片10和第二芯片20键合，非晶硅键合层106键合可以连接第一芯片10和第二芯片20，并获得如图21所示的半导体装置。In the case that the thickness of the bonding layer is greater than a predetermined threshold (eg, the depth of the first opening 104 ), for example, in the case that the deposited thickness of the amorphous silicon bonding layer 106 is sufficient to fill up the first opening 104 . As shown in FIG. 21, for step S3, the deposited amorphous silicon bonding layer 106 can be polished until the surface of the amorphous silicon bonding layer is flush with the surface of the first substrate, and then the first The chip 10 and the second chip 20 are bonded, and the bonding of the amorphous silicon bonding layer 106 can connect the first chip 10 and the second chip 20, and obtain a semiconductor device as shown in FIG. 21 .

其中，所述在所述第一绝缘层的所述第一开口对应的位置，对键合后的所述第二芯片进行刻蚀，在所述第二芯片表面形成暴露出所述第一开口的第三开口，步骤之后还包括：在所述第一绝缘层的所述第一开口对应的位置，对所述非晶硅键合层进行刻蚀，暴露出所述第一电连接层。沉积非晶硅键合层后，还需要刻蚀第一开口底部的非晶硅键合层，以便暴露出开口底部连接的第一电连接层，以形成电连接。Wherein, at the position corresponding to the first opening of the first insulating layer, the bonded second chip is etched, and the first opening is exposed on the surface of the second chip. After the step, the step further includes: etching the amorphous silicon bonding layer at a position corresponding to the first opening of the first insulating layer to expose the first electrical connection layer. After the amorphous silicon bonding layer is deposited, the amorphous silicon bonding layer at the bottom of the first opening needs to be etched to expose the first electrical connection layer connected to the bottom of the opening to form an electrical connection.

即，针对步骤S5，在刻蚀第三开口205之后，可以将第一开口10内的非晶硅键合层106刻蚀掉，以暴露出第一开口104底部的第一电连接层1022。That is, for step S5 , after etching the third opening 205 , the amorphous silicon bonding layer 106 in the first opening 10 may be etched away to expose the first electrical connection layer 1022 at the bottom of the first opening 104 .

需要说明的是，后续有关制作硅通孔形成电连接以及其他相关方面的相关描述，还可以 对应参考上述实施例步骤S4-步骤S8的相关描述，本申请实施例暂不赘述。It should be noted that, for subsequent descriptions related to fabricating through-silicon vias to form electrical connections and other related aspects, reference may also be made to the relevant descriptions of steps S4-S8 in the above-mentioned embodiments, which will not be repeated in the embodiments of the present application.

另外，基于上述三种制作半导体装置的方法，在第一电连接层的材质包括铜时，该半导体装置还可以在键合层的连接的情况下通过添加刻蚀停止层实现避免铜反溅射的问题。其中，本申请实施例以图13所示的刻蚀停止层的制作方法，示例性的说明，请参考附图23至附图25，图23是本申请实施例提供的一组基于上述方式一的半导体截面图，图24是本申请实施例提供的一组基于上述方式二的半导体截面图，图25是本申请实施例提供的一组基于上述方式三的半导体截面图。In addition, based on the above three methods of manufacturing a semiconductor device, when the material of the first electrical connection layer includes copper, the semiconductor device can also avoid copper back-sputtering by adding an etching stop layer when the bonding layer is connected. The problem. Among them, the embodiment of the present application uses the method for fabricating the etching stop layer shown in FIG. 13. For exemplary description, please refer to the accompanying drawings 23 to 25. FIG. Figure 24 is a set of semiconductor cross-sectional views based on the above-mentioned method 2 provided by the embodiment of the present application, and Figure 25 is a set of semiconductor cross-sectional views based on the above-mentioned method 3 provided by the embodiment of the present application.

基于方式一，在制作第一开口前制作键合层的情况下，如图23中(1)所示：在对第一绝缘层103和非晶硅键合层106刻蚀，并在非晶硅键合层106表面形成暴露出第一电连接层1022的第一开口104；如图23中(2)所示：在第一开口104底部沉积刻蚀停止层105，其中，有关制作刻蚀停止层105的相关描述可以对应参考图13所示的相关描述，本申请实施例在此暂不赘述；如图23中(3)所示：将图23中(2)所示第一芯片10与提供好的第二芯片20键合获得键合后的半导体装置，该刻蚀停止层105位于第一开口104的底部，覆盖了因刻蚀第一开口104而暴露出的第一电连接层1022。Based on method 1, in the case of making a bonding layer before making the first opening, as shown in (1) in Figure 23: after etching the first insulating layer 103 and the bonding layer 106 of amorphous silicon, and The first opening 104 exposing the first electrical connection layer 1022 is formed on the surface of the silicon bonding layer 106; as shown in (2) in FIG. The relevant description of the stop layer 105 can refer to the relevant description shown in FIG. 13 , and the embodiment of the present application will not be repeated here; Bonding with the provided second chip 20 to obtain a bonded semiconductor device, the etching stop layer 105 is located at the bottom of the first opening 104, covering the first electrical connection layer exposed by etching the first opening 104 1022.

需要说明的是，后续有关制作硅通孔形成电连接以及其他相关方面的相关描述，还可以对应参考上述实施例步骤S4-步骤S8以及上述图16至图18的相关描述，本申请实施例暂不赘述。It should be noted that, for subsequent descriptions related to making through-silicon vias to form electrical connections and other related aspects, reference can also be made to the above-mentioned steps S4-Step S8 and the above-mentioned related descriptions in FIG. 16 to FIG. 18 . I won't go into details.

基于方式二，在制作第一开口后制作键合层，且键合层的厚度小于预设阈值的情况下，如图24中(1)所示：在对第一绝缘层103刻蚀，并在第一绝缘层103表面形成暴露出第一电连接层1022的第一开口104；如图24中(2)所示：在第一开口104底部沉积刻蚀停止层105，其中，有关制作刻蚀停止层105的相关描述可以对应参考图13所示的相关描述，本申请实施例在此暂不赘述；如图24中(3)所示：在图23中(2)所示第一芯片10的第一绝缘层103表面沉积非晶硅键合层106，该非晶硅键合层106覆盖第一开口104底部的刻蚀停止层105；如图24中(4)所示：将该第一芯片10与提供好的第二芯片20键合获得键合后的半导体装置，该第一开口104内包括了依次层叠的非晶硅键合层106和刻蚀停止层10。Based on the second method, when the bonding layer is formed after the first opening is formed, and the thickness of the bonding layer is less than the preset threshold, as shown in (1) in FIG. 24 : the first insulating layer 103 is etched, and Form the first opening 104 exposing the first electrical connection layer 1022 on the surface of the first insulating layer 103; as shown in (2) in FIG. For the relevant description of the etch stop layer 105, reference may be made to the relevant description shown in FIG. An amorphous silicon bonding layer 106 is deposited on the surface of the first insulating layer 103 of 10, and the amorphous silicon bonding layer 106 covers the etching stop layer 105 at the bottom of the first opening 104; as shown in (4) in FIG. 24 : the The first chip 10 is bonded with the provided second chip 20 to obtain a bonded semiconductor device. The first opening 104 includes sequentially stacked amorphous silicon bonding layer 106 and etching stop layer 10 .

需要说明的是，后续有关制作硅通孔形成电连接以及其他相关方面的相关描述，还可以对应参考上述实施例步骤S4-步骤S8以及上述图19至图20的相关描述，本申请实施例暂不赘述。It should be noted that, for subsequent descriptions related to making through-silicon vias to form electrical connections and other related aspects, reference can also be made to the above-mentioned steps S4-Step S8 and the above-mentioned related descriptions in FIG. 19 to FIG. 20 . I won't go into details.

基于方式三，在制作第一开口后制作键合层，且键合层的厚度大于预设阈值的情况下，如图25中(1)所示：在对第一绝缘层103刻蚀，并在第一绝缘层103表面形成暴露出第一电连接层1022的第一开口104；如图25中(2)所示：在第一开口104底部沉积刻蚀停止层105，其中，有关制作刻蚀停止层105的相关描述可以对应参考图13所示的相关描述，本申请实施例在此暂不赘述；如图25中(3)所示：在图25中(2)所示第一芯片10的第一绝缘层103表面沉积非晶硅键合层106，该非晶硅键合层106覆盖第一开口104底部的刻蚀停止层105，且由于在垂直于第一衬底101的方向上，非晶硅键合层106与刻蚀停止层105的厚度之和大于第一开口104的深度，所以在沉积非晶硅键合层106后还需要进行抛光直至所述非晶硅键合层106的表面与所述第一衬底101表面平齐；如图25中(4)所示：将抛光后的第一芯片10与提供好的第二芯片20键合获得键合后的半导体装置，该第一开口104内包括 了依次层叠的非晶硅键合层106和刻蚀停止层10。Based on the third method, when the bonding layer is formed after the first opening is formed, and the thickness of the bonding layer is greater than the preset threshold, as shown in (1) in FIG. 25 : the first insulating layer 103 is etched, and Form the first opening 104 exposing the first electrical connection layer 1022 on the surface of the first insulating layer 103; as shown in (2) in FIG. For the relevant description of the etch stop layer 105, reference may be made to the relevant description shown in FIG. An amorphous silicon bonding layer 106 is deposited on the surface of the first insulating layer 103 of 10, and the amorphous silicon bonding layer 106 covers the etching stop layer 105 at the bottom of the first opening 104, and since the Above, the sum of the thicknesses of the amorphous silicon bonding layer 106 and the etch stop layer 105 is greater than the depth of the first opening 104, so after depositing the amorphous silicon bonding layer 106, polishing is required until the amorphous silicon bonding layer 106 is deposited. The surface of the layer 106 is flush with the surface of the first substrate 101; as shown in (4) in Figure 25: the polished first chip 10 is bonded with the provided second chip 20 to obtain a bonded semiconductor device, the first opening 104 includes sequentially stacked amorphous silicon bonding layer 106 and etching stop layer 10 .

需要说明的是，后续有关制作硅通孔形成电连接以及其他相关方面的相关描述，还可以对应参考上述实施例步骤S4-步骤S8以及上述图21至图22的相关描述，本申请实施例暂不赘述。It should be noted that, for subsequent descriptions related to making through-silicon vias to form electrical connections and other related aspects, reference can also be made to the above-mentioned steps S4-Step S8 and the above-mentioned related descriptions in FIG. 21 to FIG. 22 . I won't go into details.

进一步的，半导体装置不仅仅可以堆叠两个芯片，还可以根据业务需求，堆叠两个以上的芯片。本申请实施例以堆叠三个芯片为例，示例性的说明本申请实施例提供的一种半导体装置的制作方法。Furthermore, the semiconductor device can not only stack two chips, but also stack more than two chips according to business requirements. The embodiment of the present application takes stacking three chips as an example to exemplarily describe a method for manufacturing a semiconductor device provided in the embodiment of the present application.

首先，需要说明的是，有关第一芯片和第二芯片堆叠制作半导体装置的相关流程可以对应参考上述图1所述实施例，本申请实施例在此不再赘述。First of all, it should be noted that for the related process of stacking the first chip and the second chip to manufacture the semiconductor device, reference may be made to the above-mentioned embodiment in FIG. 1 , and details will not be repeated here in this embodiment.

其次，在上述图12所示的半导体装置的基础上，堆叠第三芯片的相关流程如下：Secondly, on the basis of the above-mentioned semiconductor device shown in FIG. 12 , the related process of stacking the third chip is as follows:

在键合后的所述第二芯片远离所述第一芯片的一侧形成第三互连层，步骤之后还包括：Forming a third interconnection layer on the side of the bonded second chip away from the first chip, after the step, also includes:

步骤S81：在第三互连层远离所述第二芯片的一侧形成第六绝缘层，请参考附图26，图26是本申请实施例提供的又一组半导体装置的截面图。如图26中(1)所示第三互连层209远离第二芯片的一侧有第六绝缘层301。Step S81: Form a sixth insulating layer on the side of the third interconnection layer away from the second chip. Please refer to FIG. 26 , which is a cross-sectional view of another set of semiconductor devices provided by an embodiment of the present application. As shown in (1) in FIG. 26 , there is a sixth insulating layer 301 on the side of the third interconnection layer 209 away from the second chip.

步骤S82：对第六绝缘层进行刻蚀，在所述第六绝缘层表面形成暴露出所述第三电连接层的第二开口。其中，如图26中(2)所示，该第六绝缘层301有暴露出所述第三电连接层2091的第二开口302。刻蚀第二开口302的方法还可以对应参考上述图1所述实施例中口渴时第一开口104的相关描述，本申请实施例不再赘述。Step S82: Etching the sixth insulating layer to form a second opening exposing the third electrical connection layer on the surface of the sixth insulating layer. Wherein, as shown in (2) in FIG. 26 , the sixth insulating layer 301 has a second opening 302 exposing the third electrical connection layer 2091 . The method of etching the second opening 302 can also refer to the relevant description of the first opening 104 when thirsty in the above-mentioned embodiment shown in FIG. 1 , which will not be repeated in this embodiment of the present application.

步骤S83：提供第三芯片，所述第三芯片包括第三衬底、第四互连层和第七绝缘层，所述第四互连层包括第八绝缘层和第四电连接层。请参考附图27，图27是本申请实施例提供的一种第三芯片的截面图。如图27所示，第三芯片30包括第三衬底401、第四互连层402和第七绝缘层403，所述第四互连层402包括第八绝缘层4021和第四电连接层4022。Step S83: providing a third chip, the third chip includes a third substrate, a fourth interconnection layer and a seventh insulating layer, and the fourth interconnection layer includes an eighth insulating layer and a fourth electrical connection layer. Please refer to FIG. 27 , which is a cross-sectional view of a third chip provided by an embodiment of the present application. As shown in Figure 27, the third chip 30 includes a third substrate 401, a fourth interconnection layer 402 and a seventh insulating layer 403, and the fourth interconnection layer 402 includes an eighth insulating layer 4021 and a fourth electrical connection layer 4022.

步骤S84：将第三芯片与上述具有第二开口的第六绝缘层键合，其中，所述第三芯片以背对的方式层叠在所述第六绝缘层远离所述第三互连层的一侧。请参考附图28，图28是本申请实施例提供的又一组半导体装置的截面图。将第三芯片30与上述具有第二开口302的第六绝缘层301键合，获得如图28中(1)所示的半导体装置。Step S84: bonding the third chip to the sixth insulating layer having the second opening, wherein the third chip is stacked on the side of the sixth insulating layer away from the third interconnection layer in a back-to-back manner. side. Please refer to FIG. 28 , which is a cross-sectional view of another set of semiconductor devices provided by an embodiment of the present application. The third chip 30 is bonded to the sixth insulating layer 301 having the second opening 302 to obtain a semiconductor device as shown in (1) in FIG. 28 .

可选的，在将第三芯片键合至如上述图26中(2)所示的半导体装置之前，还需要对第三芯片的第三衬底减薄，其具体的实现方式可以对应参考上述步骤S4的相关描述，本申请实施例不再赘述。Optionally, before bonding the third chip to the semiconductor device shown in (2) in FIG. 26 above, it is also necessary to thin the third substrate of the third chip. The relevant description of step S4 is not repeated in this embodiment of the present application.

步骤S85：在第二开口对应的位置，对键合后的第三芯片进行刻蚀，在第三芯片表面形成暴露出第二开口的第四开口，其中，所述第二开口的开口区域在所述第四开口的开口区域中。Step S85: Etching the bonded third chip at the position corresponding to the second opening, forming a fourth opening exposing the second opening on the surface of the third chip, wherein the opening area of the second opening is In the opening area of the fourth opening.

步骤S86：在第二开口处和第四开口处形成硅通孔。如图28中(2)所示，该半导体装置在第二开口处和第四开口处形成了硅通孔404，以及硅通孔绝缘层405。Step S86: forming TSVs at the second opening and the fourth opening. As shown in (2) of FIG. 28 , in the semiconductor device, TSVs 404 and TSV insulating layers 405 are formed at the second opening and the fourth opening.

该硅通孔404包括相连的第三段硅通孔和第四段硅通孔；所述第三段硅通孔为所述第二开口处形成的硅通孔，所述第三段硅通孔的底部连接所述第三电连接层；所述第四段硅通孔为所述第四开口处形成的硅通孔，贯穿所述第三芯片，所述第四段硅通孔的底部连接所述第三段硅通孔，顶部连接所述第五电连接层。其中，步骤S85-步骤S86具体的实现方式可以对应参考上述步骤S5-步骤S6的相关描述，本申请实施例不再赘述。The TSV 404 includes a connected third TSV and a fourth TSV; the third TSV is a TSV formed at the second opening, and the third TSV is a TSV formed at the second opening. The bottom of the hole is connected to the third electrical connection layer; the fourth section of through-silicon via is a through-silicon via formed at the fourth opening, which runs through the third chip, and the bottom of the fourth section of through-silicon via The third segment of TSV is connected, and the top is connected to the fifth electrical connection layer. Wherein, for the specific implementation manners of step S85-step S86, reference may be made to the relevant descriptions of the above-mentioned steps S5-step S6, which will not be repeated in this embodiment of the present application.

可选的，所述第四段硅通孔在所述第一衬底上的投影覆盖所述第三段硅通孔在所述第二 衬底上的投影。需要说明的是，该投影分别指的是在第四段硅通孔和第三段硅通孔上在连接处分别对应的区域在第二衬底上的投影。即，第四段硅通孔与第三段硅通孔连接处对应第四段硅通孔连接面的在所述第二衬底上的投影；第三段硅通孔与第四段硅通孔连接处对应第三段硅通孔连接面的在所述第二衬底上的投影。例如：第四段硅通孔与第三段硅通孔连接处中对应第四段硅通孔连接面的在所述第二衬底上的投影、覆盖了所述第三段硅通孔与第四段硅通孔的连接处中对应第三段硅通孔连接面的在所述第二衬底上的投影。Optionally, the projection of the fourth section of TSVs on the first substrate covers the projection of the third section of TSVs on the second substrate. It should be noted that the projections respectively refer to the projections on the second substrate of regions corresponding to the connection points of the fourth TSV and the third TSV respectively. That is, the connection between the fourth section of TSV and the third section of TSV corresponds to the projection of the connecting surface of the fourth section of TSV on the second substrate; the third section of TSV and the fourth section of TSV The connection of the hole corresponds to the projection of the connecting surface of the third segment of the TSV on the second substrate. For example: the projection on the second substrate corresponding to the connecting surface of the fourth TSV at the junction of the fourth TSV and the third TSV covers the third TSV and the third TSV. The connection of the fourth section of TSV corresponds to the projection of the connection surface of the third section of TSV on the second substrate.

可选的，所述第三段硅通孔的第三端连接所述第四段硅通孔的第四端，且第四端所在的区域覆盖第三端所在的区域。其中，所述第三端为所述第三段硅通孔的且远离第三电连接层的一端，所述第四端为第四段硅通孔的且靠近所述第六绝缘层的一端。在本申请实施例中，第四端所在的区域覆盖第三端所在的区域，即，所述第三段硅通孔要小于第四段硅通孔，以便在后续第三段硅通孔和第四段硅通孔填充时，不易产生空洞，避免了漏电流变大的问题，保障了半导体装置的性能。Optionally, the third end of the third section of TSV is connected to the fourth end of the fourth section of TSV, and the area where the fourth end is located covers the area where the third end is located. Wherein, the third end is an end of the third section of TSV and away from the third electrical connection layer, and the fourth end is an end of the fourth section of TSV close to the sixth insulating layer . In the embodiment of the present application, the area where the fourth end is located covers the area where the third end is located, that is, the third section of TSVs is smaller than the fourth section of TSVs, so that the subsequent third section of TSVs and TSVs When the fourth stage of TSV is filled, it is not easy to generate voids, which avoids the problem of increased leakage current and ensures the performance of the semiconductor device.

步骤S87：对第七绝缘层进行刻蚀并填充第二导电材料形成第二金属通孔，第二金属通孔的底部连接第四电连接层。请参考附图29，图29是本申请实施例提供的又一种半导体装置的截面图。如图29所示，第七绝缘层403进行刻蚀并填充第二导电材料形成第二金属通孔407，第二金属通孔407的底部连接第四电连接层4022。其中，具体的实现方式可以对应参考上述步骤S7的相关描述，本申请实施例不再赘述。Step S87: Etching the seventh insulating layer and filling the second conductive material to form a second metal via, the bottom of the second metal via is connected to the fourth electrical connection layer. Please refer to FIG. 29 , which is a cross-sectional view of another semiconductor device provided by an embodiment of the present application. As shown in FIG. 29 , the seventh insulating layer 403 is etched and filled with the second conductive material to form a second metal via 407 , and the bottom of the second metal via 407 is connected to the fourth electrical connection layer 4022 . Wherein, for a specific implementation manner, reference may be made to the relevant description of the above step S7, which will not be repeated in this embodiment of the present application.

步骤S88：在键合后的第三芯片上形成第五互连层，所述第五互连层包括第九绝缘层和第五电连接层，所述第五互连层层叠在所述第三芯片远离所述第六绝缘层的一侧。如图29所示，键合后的第三芯片30上形成第五互连层406，第五互连层406包括第九绝缘层4062和第五电连接层4061，第九绝缘层4062中嵌设有第五电连接层4061，第二金属通孔407的底部连接第四电连接层4022，顶部连接第五电连接层4061。其中，具体的实现方式可以对应参考上述步骤S8的相关描述，本申请实施例不再赘述。Step S88: forming a fifth interconnection layer on the bonded third chip, the fifth interconnection layer including a ninth insulating layer and a fifth electrical connection layer, the fifth interconnection layer stacked on the first The side of the three chips away from the sixth insulating layer. As shown in FIG. 29, a fifth interconnection layer 406 is formed on the bonded third chip 30, the fifth interconnection layer 406 includes a ninth insulating layer 4062 and a fifth electrical connection layer 4061, and the ninth insulating layer 4062 is embedded in A fifth electrical connection layer 4061 is provided, the bottom of the second metal via 407 is connected to the fourth electrical connection layer 4022 , and the top is connected to the fifth electrical connection layer 4061 . Wherein, for a specific implementation manner, reference may be made to the relevant description of the above step S8, which will not be repeated in this embodiment of the present application.

另外，如图29所示，堆叠后的半导体装置，第一电连接层1022、第二电连接层2022和第四电连接层4022通过硅通孔207和硅通孔404、第一金属通孔208、第二金属通孔407、第三电连接层2091和第五电连接层4061形成电连接。In addition, as shown in FIG. 29, in the stacked semiconductor device, the first electrical connection layer 1022, the second electrical connection layer 2022, and the fourth electrical connection layer 4022 pass through silicon vias 207, TSVs 404, and first through metal vias. 208 , the second metal via 407 , the third electrical connection layer 2091 and the fifth electrical connection layer 4061 form an electrical connection.

需要说明的是，上述实施例是在图12所示的半导体装置的基础上堆叠第三芯片构成的半导体装置，本申请实施例并不仅限制于图12所示的半导体装置，例如：还可以在包括如刻蚀停止层、键合层的半导体装置的基础上堆叠第三芯片构成的半导体装置。本申请实施例不在赘述。It should be noted that the above-mentioned embodiment is a semiconductor device formed by stacking a third chip on the basis of the semiconductor device shown in FIG. 12 . The embodiment of the present application is not limited to the semiconductor device shown in FIG. A semiconductor device formed by stacking a third chip on the basis of a semiconductor device including an etch stop layer and a bonding layer. The embodiment of this application will not be described in detail.

还需要说明的是，针对第二开口和第四开口的相关描述可以对应参考上述实施例中针对第一开口和第三开口的相关描述；针对第第六绝缘层的的相关描述可以对应参考上述实施例中针对第一绝缘层的相关描述，本申请实施例不在赘述。It should also be noted that, for the relevant description of the second opening and the fourth opening, reference may be made to the relevant description of the first opening and the third opening in the above embodiment; for the relevant description of the sixth insulating layer, reference may be made to the above-mentioned The relevant description of the first insulating layer in the embodiment will not be repeated in the embodiment of the present application.

基于上述所示的制作方法，本申请实施例还提供了一种半导体装置，包括：Based on the manufacturing method shown above, the embodiment of the present application also provides a semiconductor device, including:

第一芯片，所述第一芯片包括依次层叠的第一衬底、第一互连层和具有第一开口的第一绝缘层，所述第一互连层包括第二绝缘层和第一电连接层；所述第一开口暴露出所述第一电连接层，所述第一绝缘层为无机绝缘材料。A first chip, the first chip includes a first substrate, a first interconnection layer and a first insulating layer with a first opening stacked in sequence, the first interconnection layer includes a second insulating layer and a first electrical A connection layer; the first opening exposes the first electrical connection layer, and the first insulating layer is an inorganic insulating material.

第二芯片，所述第二芯片包括依次层叠的第二衬底、第二互连层和第三绝缘层，所述第二互连层包括第四绝缘层和第二电连接层，其中，所述第二芯片以背对的方式层叠在所述第一绝缘层上。The second chip, the second chip includes a second substrate, a second interconnection layer and a third insulating layer stacked in sequence, the second interconnection layer includes a fourth insulating layer and a second electrical connection layer, wherein, The second chips are laminated on the first insulating layer in a back-to-back manner.

第三互连层，所述第三互连层包括第五绝缘层和第三电连接层，所述第三互连层层叠于所述第二芯片远离所述第一芯片一侧。A third interconnection layer, the third interconnection layer includes a fifth insulating layer and a third electrical connection layer, and the third interconnection layer is stacked on a side of the second chip away from the first chip.

硅通孔，所述硅通孔包括相连的第一段硅通孔和第二段硅通孔，所述第二段硅通孔在所述第一衬底上的投影覆盖所述第一段硅通孔在所述第一衬底上的投影；所述第一段硅通孔位于所述第一开口中，所述第一段硅通孔的底部连接所述第一电连接层；所述第二段硅通孔贯穿所述第二芯片，所述第二段硅通孔的底部连接所述第一段硅通孔，顶部连接所述第三电连接层。through-silicon vias, the through-silicon vias include a connected first section of through-silicon vias and a second section of through-silicon vias, and the projection of the second section of through-silicon vias on the first substrate covers the first section The projection of the through-silicon via on the first substrate; the first section of the through-silicon via is located in the first opening, and the bottom of the first section of the through-silicon via is connected to the first electrical connection layer; The second TSV runs through the second chip, the bottom of the second TSV is connected to the first TSV, and the top is connected to the third electrical connection layer.

所述第三绝缘层中嵌设有第一金属通孔，所述第一金属通孔的底部连接所述第二电连接层，顶部连接所述第三电连接层；其中，所述第一电连接层和所述第二电连接层通过所述硅通孔、所述第一金属通孔和所述第三电连接层形成电连接。A first metal via is embedded in the third insulating layer, the bottom of the first metal via is connected to the second electrical connection layer, and the top is connected to the third electrical connection layer; wherein, the first The electrical connection layer and the second electrical connection layer are electrically connected through the through-silicon via, the first metal through-hole and the third electrical connection layer.

如图12所示，本申请第一方面实施例提供的半导体装置中硅通孔包括相连的两个部分，分别是第一段硅通孔和第二段硅通孔。其中，第一段硅通孔位于第一芯片的第一开口处，该第一开口是在第一绝缘层表面暴露出第一电连接层的开口，由于该第一开口底部暴露有第一电连接层，且第一电连接层电导率较高，所以在干法刻蚀过程中，电荷不会大量堆积在开口底部，避免了电荷在开口底部积聚而产生电场，从而大大的减小了横向刻蚀的现象；而且，在干法刻蚀过程中，同等电荷刻蚀绝缘材料的难度要大于刻蚀硅材料的难度，因此，在第一开口位于绝缘层的情况下，即，第一开口的两侧是绝缘层的情况下，会进一步的减小电荷横向刻蚀的现象，在后续硅通孔填充时，也不会产生空洞。第二段硅通孔是贯穿第二芯片的硅通孔，由于第二段硅通孔的底部连接第一段硅通孔，所以在刻蚀第二段硅通孔的过程中，第二段硅通孔对应开口的底部会连接第一开口，进而，第二段硅通孔对应的开口底部也不会存在电荷堆积，进而减小或避免了横向刻蚀现象。另外，本申请实施例中第一段硅通孔要小于第二段硅通孔，即，第二段硅通孔在所述第一衬底上的投影覆盖所述第一段硅通孔在所述第一衬底上的投影，以便在制备第一段硅通孔和第二段硅通孔时，不易产生空洞，避免了漏电流变大的问题，保障了半导体装置的性能。As shown in FIG. 12 , the TSV in the semiconductor device provided by the embodiment of the first aspect of the present application includes two connected parts, which are the first TSV section and the second TSV section. Wherein, the first section of TSV is located at the first opening of the first chip, and the first opening is an opening that exposes the first electrical connection layer on the surface of the first insulating layer. connection layer, and the conductivity of the first electrical connection layer is relatively high, so during the dry etching process, a large amount of charges will not accumulate at the bottom of the opening, which avoids the electric field generated by the accumulation of charges at the bottom of the opening, thereby greatly reducing the lateral The phenomenon of etching; moreover, in the dry etching process, the difficulty of etching the insulating material with the same charge is greater than the difficulty of etching the silicon material. Therefore, in the case where the first opening is located in the insulating layer, that is, the first opening In the case where both sides are insulating layers, the phenomenon of charge lateral etching will be further reduced, and voids will not be generated when the subsequent through-silicon vias are filled. The second TSV is a TSV that runs through the second chip. Since the bottom of the second TSV is connected to the first TSV, in the process of etching the second TSV, the second TSV The bottom of the opening corresponding to the TSV is connected to the first opening, and furthermore, there is no charge accumulation at the bottom of the opening corresponding to the second TSV, thereby reducing or avoiding the lateral etching phenomenon. In addition, in the embodiment of the present application, the first section of TSVs is smaller than the second section of TSVs, that is, the projection of the second section of TSVs on the first substrate covers the first section of TSVs. The projection on the first substrate is not easy to generate voids when preparing the first through-silicon via and the second through-silicon via, avoiding the problem of increased leakage current and ensuring the performance of the semiconductor device.

在一种可能实现的方式中，所述第一段硅通孔的第一端连接所述第二段硅通孔的第二端，且第二端所在的区域覆盖第一端所在的区域，其中，所述第一端为所述第一段硅通孔的且远离第一电连接层的一端，所述第二端为第二段硅通孔的且靠近所述第一绝缘层的一端。在本申请实施例中，第二端所在的区域覆盖第一端所在的区域，即，所述第一段硅通孔要小于第二段硅通孔，以便在后续第一段硅通孔和第二段硅通孔填充时，不易产生空洞，避免了漏电流变大的问题，保障了半导体装置的性能。In a possible implementation manner, the first end of the first TSV is connected to the second end of the second TSV, and the area where the second end is located covers the area where the first end is located, Wherein, the first end is an end of the first section of TSV and away from the first electrical connection layer, and the second end is an end of the second section of TSV close to the first insulating layer . In the embodiment of the present application, the area where the second end is located covers the area where the first end is located, that is, the first section of TSVs is smaller than the second section of TSVs, so that the subsequent first section of TSVs and TSVs When the second TSV is filled, it is not easy to generate voids, which avoids the problem of increased leakage current and ensures the performance of the semiconductor device.

在一种可能实现的方式中，在垂直于所述第一衬底的方向上，所述第一绝缘层厚度大于0微米小于或等于2微米。在本申请实施例中，随着第一绝缘层厚度的增加，在刻蚀过程中可以逐渐减小电荷堆积所产生的电场对刻蚀性离子方向的影响，从而减小或避免横向刻蚀现象。In a possible implementation manner, in a direction perpendicular to the first substrate, the thickness of the first insulating layer is greater than 0 micrometers and less than or equal to 2 micrometers. In the embodiment of the present application, as the thickness of the first insulating layer increases, the influence of the electric field generated by the charge accumulation on the direction of the etching ions can be gradually reduced during the etching process, thereby reducing or avoiding the lateral etching phenomenon .

在一种可能实现的方式中，所述第一电连接层的材质包括铜；所述装置还包括设置于所述第一开口处的刻蚀停止层，所述刻蚀停止层的底部连接所述第一电连接层，顶部连接所述第一段硅通孔。目前，在刻蚀硅通孔底部绝缘层过程中，即第一开口的刻蚀过程中为了将底部电连接层充分露出，通常会进行过刻蚀(over etch)步骤。当底部电连接层为铜Cu时，过刻蚀会导致Cu反溅射到硅通孔侧壁上，对硅通孔侧壁造成Cu污染，会引起硅通孔的击穿电压降低从而对整个硅通孔的电学性能产生负面影响。因此，在本申请实施例中，如图15A所示，在第一电连接层的材质为铜的情况下，在所述第一开口处还包括刻蚀停止层，该刻蚀停 止层可以在过刻蚀防止铜溅射，保证该硅通孔的性能。In a possible implementation manner, the material of the first electrical connection layer includes copper; the device further includes an etching stop layer disposed at the first opening, the bottom of the etching stop layer is connected to the The first electrical connection layer, the top of which is connected to the first section of TSVs. At present, in the process of etching the insulating layer at the bottom of the TSV, that is, during the etching process of the first opening, in order to fully expose the bottom electrical connection layer, an over etch step is usually performed. When the bottom electrical connection layer is copper Cu, over-etching will cause Cu back-sputtering to the sidewall of the TSV, causing Cu pollution to the sidewall of the TSV, which will cause the breakdown voltage of the TSV to decrease, thereby affecting the entire TSV. The electrical performance of TSVs is negatively affected. Therefore, in the embodiment of the present application, as shown in FIG. 15A , in the case where the material of the first electrical connection layer is copper, an etching stop layer is further included at the first opening, and the etching stop layer can be Overetching prevents copper sputtering and ensures the performance of the TSV.

在一种可能实现的方式中，在垂直于所述第一衬底方向上，所述刻蚀停止层厚度小于所述第一开口的深度。在本申请实施例中，为了保证硅通孔的电学性能，刻蚀停止层的厚度要小于形成第一段硅通孔的第一开口的深度。In a possible implementation manner, in a direction perpendicular to the first substrate, the thickness of the etching stop layer is smaller than the depth of the first opening. In the embodiment of the present application, in order to ensure the electrical performance of the through-silicon via, the thickness of the etching stop layer is smaller than the depth of the first opening forming the first section of the through-silicon via.

在一种可能实现的方式中，所述刻蚀停止层的材质包括Ni、NiMoP、NiP、NiB、Co、CoWP、Ti、Ta、TiN、TaN、TiW、Al、Cr、W、Mn或Mg中的一种。在本申请实施例中，刻蚀停止层的材质一般选择具有导电性能，且不会因为过刻蚀出现反溅射问题的金属。包括但不限于以下材质中的一种：Ni、NiMoP、NiP、NiB、Co、CoWP、Ti、Ta、TiN、TaN、TiW、Al、Cr、W、Mn、Mg。In a possible implementation manner, the material of the etching stop layer includes Ni, NiMoP, NiP, NiB, Co, CoWP, Ti, Ta, TiN, TaN, TiW, Al, Cr, W, Mn or Mg kind of. In the embodiment of the present application, the material of the etching stop layer is generally selected to be a metal that has conductive properties and does not cause anti-sputtering problems due to over-etching. Including but not limited to one of the following materials: Ni, NiMoP, NiP, NiB, Co, CoWP, Ti, Ta, TiN, TaN, TiW, Al, Cr, W, Mn, Mg.

在一种可能实现的方式中，所述装置还包括非晶硅键合层，所述非晶硅键合层设置于所述第二衬底与所述第一绝缘层之间。在本申请实施例中，如图18、图20或图22所示，除了第一芯片和第二芯片直接键合的方式，还可以通过如：非晶硅键合层、绝缘键合层等其他方式键合连接。In a possible implementation manner, the device further includes an amorphous silicon bonding layer, and the amorphous silicon bonding layer is disposed between the second substrate and the first insulating layer. In the embodiment of the present application, as shown in Fig. 18, Fig. 20 or Fig. 22, in addition to the direct bonding of the first chip and the second chip, for example, an amorphous silicon bonding layer, an insulating bonding layer, etc. Other ways to bond the connection.

在一种可能实现的方式中，在垂直与所述第一衬底方向上，所述第一衬底的厚度大于所述第二衬底的厚度。在本申请实施例中，可以根据业务需求减薄第二芯片中第二衬底的厚度，以提高硅通孔的电学性能以及减小半导体装置的体积。In a possible implementation manner, in a direction perpendicular to the first substrate, the thickness of the first substrate is greater than the thickness of the second substrate. In the embodiment of the present application, the thickness of the second substrate in the second chip can be reduced according to business requirements, so as to improve the electrical performance of the TSV and reduce the volume of the semiconductor device.

在一种可能实现的方式中，在垂直于所述第二衬底方向上，所述第二衬底的厚度大于或等于5微米且小于或等于100微米。在本申请实施例中，由于第二衬底中还可能制作有晶体管等有源器件，所以可以根据业务需求，第二衬底的厚度在5μm-100μm之间。另外，减薄第二衬底的厚度可以提高硅通孔的电学性能以及减小半导体装置的体积。In a possible implementation manner, in a direction perpendicular to the second substrate, the thickness of the second substrate is greater than or equal to 5 microns and less than or equal to 100 microns. In the embodiment of the present application, since active devices such as transistors may also be fabricated in the second substrate, the thickness of the second substrate may be between 5 μm and 100 μm according to business requirements. In addition, reducing the thickness of the second substrate can improve the electrical performance of the TSV and reduce the volume of the semiconductor device.

在一种可能实现的方式中，所述装置还包括：In a possible implementation manner, the device further includes:

具有第二开口的第六绝缘层，所述第六绝缘层层叠在所述第三互连层远离所述第二芯片的一侧，所述第二开口暴露出所述第三电连接层。A sixth insulating layer with a second opening, the sixth insulating layer is stacked on the side of the third interconnection layer away from the second chip, the second opening exposes the third electrical connection layer.

第三芯片，所述第三芯片包括依次层叠的第三衬底、第四互连层和第七绝缘层，所述第四互连层包括第八绝缘层和第四电连接层；其中，所述第三芯片以背对的方式层叠在所述第六绝缘层远离所述第三互连层的一侧。The third chip, the third chip includes a third substrate, a fourth interconnection layer and a seventh insulating layer stacked in sequence, and the fourth interconnection layer includes an eighth insulating layer and a fourth electrical connection layer; wherein, The third chip is stacked on the side of the sixth insulating layer away from the third interconnection layer in a back-to-back manner.

第五互连层，所述第五互连层包括第九绝缘层和第五电连接层，所述第五互连层层叠在所述第三芯片远离所述第六绝缘层的一侧。A fifth interconnection layer, the fifth interconnection layer including a ninth insulating layer and a fifth electrical connection layer, the fifth interconnection layer stacked on a side of the third chip away from the sixth insulating layer.

所述硅通孔还包括相连的第三段硅通孔和第四段硅通孔，所述第四段硅通孔在所述第一衬底上的投影覆盖所述第三段硅通孔在所述第二衬底上的投影；所述第三段硅通孔位于所述第二开口中，所述第三段硅通孔的底部连接所述第三电连接层；所述第四段硅通孔贯穿所述第三芯片，所述第四段硅通孔的底部连接所述第三段硅通孔，顶部连接所述第五电连接层。The TSV further includes a connected third TSV and a fourth TSV, and the projection of the fourth TSV on the first substrate covers the third TSV Projection on the second substrate; the third through-silicon via is located in the second opening, and the bottom of the third through-silicon via is connected to the third electrical connection layer; the fourth A section of through-silicon vias runs through the third chip, a bottom of the fourth section of through-silicon vias is connected to the third section of through-silicon vias, and a top is connected to the fifth electrical connection layer.

所述第八绝缘层中包括第二金属通孔，所述第二金属通孔的底部连接所述第四电连接层，顶部连接所述第五电连接层；其中，所述第一电连接层、所述第二电连接层和第四电连接层通过所述硅通孔、所述第一金属通孔、所述第二金属通孔、所述第三电连接层和所述第五电连接层形成电连接。The eighth insulating layer includes a second metal via, the bottom of the second metal via is connected to the fourth electrical connection layer, and the top is connected to the fifth electrical connection layer; wherein the first electrical connection layer, the second electrical connection layer and the fourth electrical connection layer through the silicon via, the first metal via, the second metal via, the third electrical connection layer and the fifth The electrical connection layer forms electrical connections.

如图29所示，在本申请实施例中，该半导体装置不仅仅可以堆叠两个芯片，还可以根据业务需求，通过上述方式堆叠两个以上的芯片。例如：本申请实施例的半导体装置中，可以实现第一芯片、第二芯片和第三芯片的堆叠。其中，在将第三芯片堆叠在第二芯片上时，为保证硅通孔不会因空隙影响硅通孔的电学性能，可以先刻蚀硅通孔底部绝缘层开口，减小或避免电荷堆积。同理，本申请实施例并不限制芯片堆叠的个数，可以根据业务需求，实现多 层堆叠。As shown in FIG. 29 , in the embodiment of the present application, the semiconductor device can not only stack two chips, but also stack more than two chips in the above-mentioned manner according to business requirements. For example: in the semiconductor device of the embodiment of the present application, stacking of the first chip, the second chip and the third chip can be realized. Wherein, when the third chip is stacked on the second chip, in order to ensure that the electrical performance of the TSV will not be affected by the gap, the insulating layer opening at the bottom of the TSV can be etched first to reduce or avoid charge accumulation. Similarly, the embodiment of the present application does not limit the number of chip stacks, and multi-layer stacking can be realized according to business requirements.

需要说明的是，本申请实施例中所涉及的半导体装置还可以对应参考上述图2-图29所示的实施例。It should be noted that, for the semiconductor devices involved in the embodiments of the present application, reference may also be made to the embodiments shown in FIGS. 2-29 above.

在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可能可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本申请所必须的。It should be noted that for the foregoing method embodiments, for the sake of simple description, they are expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the described action sequence. Depending on the application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification belong to preferred embodiments, and the actions and modules involved are not necessarily required by this application.

在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如上述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。In the several embodiments provided in this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the above units is only a logical function division. In actual implementation, there may be other division methods, for example, multiple units or components can be combined or integrated. to another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical or other forms.

上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

另外，在本申请各实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

上述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以为个人计算机、服务端或者网络设备等，具体可以是计算机设备中的处理器)执行本申请各个实施例上述方法的全部或部分步骤。其中，而前述的存储介质可包括：U盘、移动硬盘、磁碟、光盘、只读存储器(Read-Only Memory，缩写：ROM)或者随机存取存储器(Random Access Memory，缩写：RAM)等各种可以存储程序代码的介质。If the above integrated units are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, server or network device, etc., specifically, a processor in the computer device) execute all or part of the steps of the above-mentioned methods in various embodiments of the present application. Wherein, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disc, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and the like. A medium on which program code can be stored.

以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still understand the foregoing The technical solutions recorded in each embodiment are modified, or some of the technical features are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the application.

1. 一种半导体装置，其特征在于，所述装置包括：A semiconductor device, characterized in that the device comprises:

   第一芯片，所述第一芯片包括依次层叠的第一衬底、第一互连层和具有第一开口的第一绝缘层，所述第一互连层包括第二绝缘层和第一电连接层；所述第一开口暴露出所述第一电连接层，所述第一绝缘层为无机绝缘材料；A first chip, the first chip includes a first substrate, a first interconnection layer and a first insulating layer with a first opening stacked in sequence, the first interconnection layer includes a second insulating layer and a first electrical A connection layer; the first opening exposes the first electrical connection layer, and the first insulating layer is an inorganic insulating material;

   第二芯片，所述第二芯片包括依次层叠的第二衬底、第二互连层和第三绝缘层，所述第二互连层包括第四绝缘层和第二电连接层，其中，所述第二芯片以背对的方式层叠在所述第一绝缘层上；The second chip, the second chip includes a second substrate, a second interconnection layer and a third insulating layer stacked in sequence, the second interconnection layer includes a fourth insulating layer and a second electrical connection layer, wherein, The second chip is laminated on the first insulating layer in a back-to-back manner;

   第三互连层，所述第三互连层包括第五绝缘层和第三电连接层，所述第三互连层层叠于所述第二芯片远离所述第一芯片一侧；A third interconnection layer, the third interconnection layer including a fifth insulating layer and a third electrical connection layer, the third interconnection layer being stacked on a side of the second chip away from the first chip;

   硅通孔，所述硅通孔包括相连的第一段硅通孔和第二段硅通孔，所述第二段硅通孔在所述第一衬底上的投影覆盖所述第一段硅通孔在所述第一衬底上的投影；所述第一段硅通孔位于所述第一开口中，所述第一段硅通孔的底部连接所述第一电连接层；所述第二段硅通孔贯穿所述第二晶圆，所述第二段硅通孔的底部连接所述第一段硅通孔，顶部连接所述第三电连接层。through-silicon vias, the through-silicon vias include a connected first section of through-silicon vias and a second section of through-silicon vias, and the projection of the second section of through-silicon vias on the first substrate covers the first section The projection of the through-silicon via on the first substrate; the first section of the through-silicon via is located in the first opening, and the bottom of the first section of the through-silicon via is connected to the first electrical connection layer; The second TSV runs through the second wafer, the bottom of the second TSV is connected to the first TSV, and the top is connected to the third electrical connection layer.

2. 根据权利要求1所述装置，其特征在于，所述装置还包括非晶硅键合层，所述非晶硅键合层设置于所述第二衬底与所述第一绝缘层之间。The device according to claim 1, further comprising an amorphous silicon bonding layer disposed between the second substrate and the first insulating layer.

3. 根据权利要求1或2所述装置，其特征在于，所述第一电连接层的材质包括铜；所述装置还包括设置于所述第一开口处的刻蚀停止层，所述刻蚀停止层的底部连接所述第一电连接层，顶部连接所述第一段硅通孔。The device according to claim 1 or 2, wherein the material of the first electrical connection layer includes copper; the device further comprises an etching stop layer disposed at the first opening, and the etching stop The bottom of the layer is connected to the first electrical connection layer, and the top of the layer is connected to the first section of through-silicon vias.

4. 根据权利要求3所述装置，其特征在于，所述刻蚀停止层的材质包括Ni、NiMoP、NiP、NiB、Co、CoWP、Ti、Ta、TiN、TaN、TiW、Al、Cr、W、Mn或Mg中的一种。The device according to claim 3, wherein the material of the etching stop layer comprises Ni, NiMoP, NiP, NiB, Co, CoWP, Ti, Ta, TiN, TaN, TiW, Al, Cr, W, Mn Or one of Mg.

5. 根据权利要求3或4所述装置，其特征在于，在垂直于所述第一衬底方向上，所述刻蚀停止层厚度小于所述第一开口的深度。The device according to claim 3 or 4, characterized in that, in a direction perpendicular to the first substrate, the thickness of the etching stop layer is smaller than the depth of the first opening.

6. 根据权利要求1-5所述任意一项装置，其特征在于，在垂直与所述第一衬底方向上，所述第一衬底的厚度大于所述第二衬底的厚度。The device according to any one of claims 1-5, characterized in that, in a direction perpendicular to the first substrate, the thickness of the first substrate is greater than the thickness of the second substrate.

7. 根据权利要求1-6所述任意一项装置，其特征在于，所述第三绝缘层中嵌设有第一金属通孔，所述第一金属通孔的底部连接所述第二电连接层，顶部连接所述第三电连接层；其中，所述第一电连接层和所述第二电连接层通过所述硅通孔、所述第一金属通孔和所述第三电连接层形成电连接。The device according to any one of claims 1-6, wherein a first metal via is embedded in the third insulating layer, and the bottom of the first metal via is connected to the second electrical connection layer , the top is connected to the third electrical connection layer; wherein, the first electrical connection layer and the second electrical connection layer pass through the silicon via, the first metal via and the third electrical connection layer Make an electrical connection.

8. 根据权利要求1-7所述任意一项装置，其特征在于，所述装置还包括：The device according to any one of claims 1-7, wherein the device further comprises:

   具有第二开口的第六绝缘层，所述第六绝缘层层叠在所述第五绝缘层远离所述第二芯片 的一侧，所述第二开口暴露出所述第三电连接层；A sixth insulating layer with a second opening, the sixth insulating layer is stacked on the side of the fifth insulating layer away from the second chip, the second opening exposes the third electrical connection layer;

   第三芯片，所述第三芯片包括依次层叠的第三衬底、第四互连层和第七绝缘层，所述第四互连层包括第八绝缘层和第四电连接层；其中，所述第三芯片以背对的方式层叠在所述第六绝缘层远离所述第五绝缘层的一侧；The third chip, the third chip includes a third substrate, a fourth interconnection layer and a seventh insulating layer stacked in sequence, and the fourth interconnection layer includes an eighth insulating layer and a fourth electrical connection layer; wherein, The third chip is laminated on the side of the sixth insulating layer away from the fifth insulating layer in a back-to-back manner;

   第五互连层，所述第五互连层包括第九绝缘层和第五电连接层，所述第五互连层层叠在所述第三芯片远离所述第六绝缘层的一侧；A fifth interconnection layer, the fifth interconnection layer including a ninth insulating layer and a fifth electrical connection layer, the fifth interconnection layer being stacked on the side of the third chip away from the sixth insulating layer;

   所述硅通孔还包括相连的第三段硅通孔和第四段硅通孔，所述第四段硅通孔在所述第一衬底上的投影覆盖所述第三段硅通孔在所述第二衬底上的投影；所述第三段硅通孔位于所述第二开口中，所述第三段硅通孔的底部连接所述第三电连接层；所述第四段硅通孔贯穿所述第三芯片，所述第四段硅通孔的底部连接所述第三段硅通孔，顶部连接所述第五电连接层；The TSV further includes a connected third TSV and a fourth TSV, and the projection of the fourth TSV on the first substrate covers the third TSV Projection on the second substrate; the third through-silicon via is located in the second opening, and the bottom of the third through-silicon via is connected to the third electrical connection layer; the fourth A section of through-silicon vias runs through the third chip, the bottom of the fourth section of through-silicon vias is connected to the third section of through-silicon vias, and the top is connected to the fifth electrical connection layer;

   所述第八绝缘层中包括第二金属通孔，所述第二金属通孔的底部连接所述第四电连接层，顶部连接所述第五电连接层；其中，所述第一电连接层、所述第二电连接层和第四电连接层通过所述硅通孔、所述第一金属通孔、所述第二金属通孔、所述第三电连接层和所述第五电连接层形成电连接。The eighth insulating layer includes a second metal via, the bottom of the second metal via is connected to the fourth electrical connection layer, and the top is connected to the fifth electrical connection layer; wherein the first electrical connection layer, the second electrical connection layer and the fourth electrical connection layer through the silicon via, the first metal via, the second metal via, the third electrical connection layer and the fifth The electrical connection layer forms electrical connections.

9. 一种半导体装置的制作方法，其特征在于，所述方法包括：A method for manufacturing a semiconductor device, characterized in that the method comprises:

   提供第一芯片，所述第一芯片包括依次层叠的第一衬底、第一互连层和第一绝缘层，所述第一互连层包括第二绝缘层和第一电连接层；providing a first chip, the first chip comprising a first substrate, a first interconnection layer and a first insulating layer stacked in sequence, the first interconnection layer comprising a second insulating layer and a first electrical connection layer;

   对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，所述第一绝缘层为无机绝缘材料；Etching the first insulating layer, forming a first opening exposing the first electrical connection layer on the surface of the first insulating layer, the first insulating layer is an inorganic insulating material;

   提供第二芯片，所述第二芯片包括依次层叠的第二衬底、第二互连层和第三绝缘层，所述第二互连层包括第四绝缘层和第二电连接层；providing a second chip, the second chip comprising a second substrate, a second interconnection layer and a third insulating layer stacked in sequence, the second interconnection layer comprising a fourth insulating layer and a second electrical connection layer;

   将所述第一芯片与所述第二芯片键合，其中，所述第二芯片以背对的方式层叠在所述第一绝缘层上；bonding the first chip to the second chip, wherein the second chip is laminated on the first insulating layer in a back-to-back manner;

   在所述第一开口对应的位置，对键合后的所述第二芯片进行刻蚀，在所述第二芯片表面形成暴露出所述第一开口的第三开口；Etching the bonded second chip at a position corresponding to the first opening, forming a third opening exposing the first opening on the surface of the second chip;

   在所述第一开口处和所述第三开口处形成硅通孔。Through silicon vias are formed at the first opening and the third opening.

10. 根据权利要求9所述方法，其特征在于，所述第一电连接层的材质包括铜；The method according to claim 9, wherein the material of the first electrical connection layer comprises copper;

    所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，步骤之后还包括：After the step of etching the first insulating layer and forming a first opening exposing the first electrical connection layer on the surface of the first insulating layer, the step further includes:

    在所述第一绝缘层的所述第一开口内的所述第一电连接层上形成刻蚀停止层，其中，在垂直于所述第一衬底方向上，所述刻蚀停止层厚度小于所述第一开口的深度。An etch stop layer is formed on the first electrical connection layer in the first opening of the first insulating layer, wherein, in a direction perpendicular to the first substrate, the thickness of the etch stop layer is less than the depth of the first opening.

11. 根据权利要求10所述方法，其特征在于，所述刻蚀停止层的材质包括Ni、NiMoP、NiP、NiB、Co、CoWP、Ti、Ta、TiN、TaN、TiW、Al、Cr、W、Mn或Mg中的一种。The method according to claim 10, wherein the material of the etching stop layer comprises Ni, NiMoP, NiP, NiB, Co, CoWP, Ti, Ta, TiN, TaN, TiW, Al, Cr, W, Mn Or one of Mg.

12. 根据权利要求9-11所述任意一项方法，其特征在于，所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，步骤之前还包括：The method according to any one of claims 9-11, wherein the first insulating layer is etched to form a first insulating layer exposing the first electrical connection layer on the surface of the first insulating layer. Before an opening, the steps also include:

    在所述第一绝缘层表面上沉积覆盖非晶硅键合层；depositing a covering amorphous silicon bonding layer on the surface of the first insulating layer;

    所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层 的第一开口的步骤，包括：The step of etching the first insulating layer and forming a first opening exposing the first electrical connection layer on the surface of the first insulating layer includes:

    对所述第一绝缘层和所述非晶硅键合层进行刻蚀，在所述非晶硅键合层表面形成暴露出所述第一电连接层的所述第一开口。The first insulating layer and the amorphous silicon bonding layer are etched, and the first opening exposing the first electrical connection layer is formed on the surface of the amorphous silicon bonding layer.

13. 根据权利要求9-11所述任意一项方法，其特征在于，所述对所述第一绝缘层进行刻蚀，在所述第一绝缘层表面形成暴露出所述第一电连接层的第一开口，步骤之后还包括：The method according to any one of claims 9-11, wherein the first insulating layer is etched to form a first insulating layer exposing the first electrical connection layer on the surface of the first insulating layer. As soon as you open your mouth, after the steps also include:

    在所述第一绝缘层表面上沉积覆盖非晶硅键合层；depositing a covering amorphous silicon bonding layer on the surface of the first insulating layer;

    在垂直于所述第一衬底方向上，所述非晶硅键合层的厚度大于所述第一开口的深度时，对所述非晶硅键合层进行抛光直至所述非晶硅键合层的表面与所述第一衬底表面平齐。In the direction perpendicular to the first substrate, when the thickness of the amorphous silicon bonding layer is greater than the depth of the first opening, the amorphous silicon bonding layer is polished until the amorphous silicon bond The surface of the composite layer is flush with the surface of the first substrate.

14. 根据权利要求12或13所述方法，其特征在于，所述在所述第一绝缘层的所述第一开口对应的位置，对键合后的所述第二芯片进行刻蚀，在所述第二芯片表面形成暴露出所述第一开口的第三开口，步骤之后还包括：The method according to claim 12 or 13, wherein the bonded second chip is etched at the position corresponding to the first opening of the first insulating layer, and the forming a third opening exposing the first opening on the surface of the second chip, and after the step, further comprising:

    在所述第一绝缘层的所述第一开口对应的位置，对所述非晶硅键合层进行刻蚀，暴露出所述第一电连接层。At a position corresponding to the first opening of the first insulating layer, the amorphous silicon bonding layer is etched to expose the first electrical connection layer.

15. 根据权利要求12-14任意一项所述方法，其特征在于，所述提供第二芯片，步骤之后还包括：The method according to any one of claims 12-14, characterized in that, after the step of providing the second chip, further comprising:

    以所述第二衬底背面向上的方式，将所述第二芯片临时键合至支撑基板，并对所述第二衬底背面进行减薄；Temporarily bonding the second chip to a supporting substrate with the back of the second substrate facing upward, and thinning the back of the second substrate;

    所述将所述第一芯片与所述第二芯片键合的步骤，包括：The step of bonding the first chip to the second chip includes:

    通过所述支撑基板，向所述第一衬底正面方向，将所述第二芯片的所述第二衬底背面与所述第一芯片的所述第一绝缘层或所述非晶硅键合层进行直接键合；Through the support substrate, the back surface of the second substrate of the second chip is bonded to the first insulating layer or the amorphous silicon of the first chip in the front direction of the first substrate. laminated layer for direct bonding;

    去除所述支撑基板。The support substrate is removed.

16. 根据权利要求9-15任意一项所述方法，其特征在于，所述在所述第一开口处和所述第三开口处形成硅通孔，步骤之后还包括：The method according to any one of claims 9-15, wherein, after the step of forming through-silicon vias at the first opening and the third opening, further comprising:

    对所述第三绝缘层进行刻蚀并填充第一导电材料，形成第一金属通孔，所述第一金属通孔的底部连接所述第二电连接层，顶部连接所述第三电连接层；Etching the third insulating layer and filling the first conductive material to form a first metal via, the bottom of the first metal via is connected to the second electrical connection layer, and the top is connected to the third electrical connection layer;

    在键合后的所述第二芯片远离所述第一芯片的一侧形成第三互连层，所述第三互连层包括第五绝缘层和第三电连接层，其中，所述第一电连接层和所述第二电连接层通过所述硅通孔、所述第一金属通孔和所述第三电连接层形成电连接。A third interconnection layer is formed on the side of the bonded second chip away from the first chip, and the third interconnection layer includes a fifth insulating layer and a third electrical connection layer, wherein the first An electrical connection layer and the second electrical connection layer are electrically connected through the through-silicon via, the first metal through-hole and the third electrical connection layer.

17. 根据权利要求9-16任意一项所述方法，其特征在于，所述在键合后的所述第二芯片远离所述第一芯片的一侧形成第五绝缘层，步骤之后还包括：The method according to any one of claims 9-16, wherein the fifth insulating layer is formed on the side of the bonded second chip away from the first chip, and after the step, further comprising:

    在第五绝缘层远离所述第二芯片的一侧形成第六绝缘层，对所述第六绝缘层进行刻蚀，在所述第六绝缘层表面形成暴露出所述第三电连接层的第二开口；Form a sixth insulating layer on the side of the fifth insulating layer away from the second chip, etch the sixth insulating layer, and form a hole on the surface of the sixth insulating layer that exposes the third electrical connection layer. second opening;

    提供第三芯片，所述第三芯片包括依次层叠的第三衬底、第四互连层和第七绝缘层，所述第四互连层包括第八绝缘层和第四电连接层；providing a third chip, the third chip comprising a third substrate, a fourth interconnection layer and a seventh insulating layer stacked in sequence, the fourth interconnection layer comprising an eighth insulating layer and a fourth electrical connection layer;

    将所述第三芯片与具有所述第二开口的所述第六绝缘层键合，其中，所述第三芯片以背对的方式层叠在所述第六绝缘层远离所述第五绝缘层的一侧；bonding the third chip to the sixth insulating layer having the second opening, wherein the third chip is stacked on the sixth insulating layer away from the fifth insulating layer in a back-to-back manner side of

    在所述第二开口对应的位置，对键合后的所述第三芯片进行刻蚀，在所述第三芯片表面形成暴露出所述第二开口的第四开口；Etching the bonded third chip at a position corresponding to the second opening, forming a fourth opening exposing the second opening on the surface of the third chip;

    在所述第二开口处和所述第四开口处形成所述硅通孔；forming the TSV at the second opening and the fourth opening;

    对所述第七绝缘层进行刻蚀并填充第二导电材料形成第二金属通孔，所述第二金属通孔的底部连接所述第四电连接层，顶部连接所述第五电连接层；Etching the seventh insulating layer and filling it with a second conductive material to form a second metal via, the bottom of the second metal via is connected to the fourth electrical connection layer, and the top is connected to the fifth electrical connection layer ;

    在键合后的所述第三芯片远离所述第六绝缘层的一侧形成第五互连层，所述第五互连层包括第九绝缘层和第五电连接层，其中，所述第一电连接层、所述第二电连接层和第四电连接层通过所述硅通孔、所述第一金属通孔、所述第二金属通孔、所述第三电连接层和所述第五电连接层形成电连接。A fifth interconnection layer is formed on the side of the bonded third chip away from the sixth insulating layer, and the fifth interconnection layer includes a ninth insulating layer and a fifth electrical connection layer, wherein the The first electrical connection layer, the second electrical connection layer and the fourth electrical connection layer pass through the silicon via, the first metal via, the second metal via, the third electrical connection layer and The fifth electrical connection layer forms an electrical connection.

18. 一种电子设备，其特征在于，包括如上述权利要求1-8任一项所述的半导体装置和电路板，所述半导体装置与所述电路板电连接。An electronic device, characterized by comprising the semiconductor device according to any one of claims 1-8 and a circuit board, the semiconductor device being electrically connected to the circuit board.