Scintilla / Bugs / #613 vhdl folding confused after instance of component

Hi

The folding mechanism gets confused by an
instance of a component if the optional keyword "component" is written before the name of the
component to instantiate.

1 architecture rtl of test is
2 component ff is
3 generic(
4 width : natural);
5 port(
6 d : in std_logic_vector;
7 q : out std_logic_vector
8 );
9 end component ff;
10 begin
11 instance : component ff
12 -- ^^^^^^^^^ is optional
13 generic map(
14 width => 8
15 )
16 port map(
17 d => d,
18 q => q
19 );
20
21 end architecture rtl;

when you fold the code on line 11 then the lines 11 to 21 will be folded.

If you remove the word "component" the folding will not be possible for the whole instance (generic map + port map).

regards daniel
danselmi at gmx.net