IBM z15

The z15 is a microprocessor made by IBM for their z15 mainframe computers, announced on September 12, 2019.^[2]

The processor unit chip (PU chip) has 12 cores. The z15 cores support two-way simultaneous multithreading.^[3]

The cores implement the CISC z/Architecture with a superscalar, out-of-order pipeline. New in z15 is an on-chip nest accelerator unit, shared by all cores, to accelerate compression.^[3]

The cache (e.g. level 3) is doubled from the previous generation z14, while the "L4 cache increased from 672MB to 960MB, or +43%" with the new add-on chip system controller (SC) SCM. Both it and all levels of cache in the main processor from level 1 use eDRAM, instead of the traditionally used SRAM. "A five-CPC drawer system has 4800 MB (5 x 960 MB) of shared L4 cache."^{[citation needed]}