Programmable Logic DesignLine | Xilinx unveil revolutionary 65nm FPGA architecture: the Virtex-5 family

Xilinx's new Virtex-5 devices are the world's first FPGAs to be fabricated at the 65 nm technology node. These devices are based on a low-K dielectric process that reduces parasitic capacitance, enables faster switching speeds, and reduces heat dissipation. Their 12-layer metallization (11 copper layers and 1 aluminum layer) supports an advanced diagonal interconnect fabric. Their core voltage has been reduced to 1.0V, thereby reducing dynamic power consumption (the core voltage of Virtex-4 devices is 1.2V). Meanwhile, their second-generation triple-oxide technology dramatically reduces static power dissipation.

Overall, the new Virtex-5 family provides 65% more logic cells and 25% more input/outputs (I/Os) as compared to the preceding Virtex-4 generation of devices. At the same time, members of the Virtex-5 family are claimed to provide 30% higher performance, 35% lower dynamic power dissipation, and they consume 45% less silicon real estate as compared to their Virtex-4 counterparts.

All members of the Virtex-5 family are based on Xilinx's ASMBL (Advanced Silicon Modular Block) architecture. For each application domain – such as digital signal processing – Xilinx has determine the optimum mixture (ratio) of logic, memory, DSP slices, and so forth. Next, for each application domain, Xilinx create a suite of components, all based on the same "mix" but with a range of capacities. This suite is collectively referred to as a "platform". Based on this, Xilinx have announced four domain-optimized platforms as follows:

• Virtex-5 LX: High performance logic (shipping now).
• Virtex-5 LXT: High performance logic with serial connectivity (coming in the second half of 2006).
• Virtex-5 SXT: High performance DSP with serial connectivity (coming in the second half of 2006).
• Virtex-5 FXT: Embedded processing with serial connectivity (coming in the first half of 2007).

Virtex-5 devices are also based on Xilinx's new ExpressFabric technology, which features LUTs with 6 independent inputs for fewer logic levels, and a new diagonal interconnect architecture that facilitates shorter, faster routing. An overview of some of the more significant Virtex-5 architectural features are as follows:

6-Input lookup tables (LUTs)
The first FPGA to be presented to the market in 1985 – the XC2064 from Xilinx – contained 64 configurable logic blocks (CLBs), each of which boasted two 3-input lookup tables (LUTS). Subsequent generations moved to 4-input LUTs, because these offered a more optimal balance with regard to logic utilization and minimizing the number of logic levels in the context of designs of that era.

However, there has been a fundamental shift in the nature of designs over recent years. Today's designs often feature wide data paths, especially in the case of digital signal processing (DSP) applications. Implementing these designs using 4-input LUTs can require many levels of logic, thereby impacting performance. In order to address this issue, the ExpressFabric employed by the Virtex-5 family feature's LUTs with six independent inputs, which can significantly reduce the number of logic levels required to implement wide functions (Fig 1).

1. The Virtex-5 family features 6-input LUTs.

Each of these logical elements can be used as a true 6-input LUT or as two 5-input LUTs that share five of their inputs. In addition to containing four 6-input LUTs, a Virtex-5 slice also includes faster flip-flops to speed pipelined designs and an improved carry chain architecture to speed arithmetic operations. Overall, Virtex-5 family provides 65% more logic cells (330,000 LCs) as compared to their Virtex-4 counterparts.

Diagonal interconnect
The traditional way of implementing FPGA interconnect results in a complex pattern as to which CLBs can be reached from an initial CLB in 1, 2, 3, or more hops. Consider the central (red) CLB shown in Fig 2 for example; from this starting point, the CLBs in yellow can be reached in 1 hop, the CLBs in green can be reached in 2 hops, and the CLBs in blue can be reached in three hops.

2. Traditional Virtex-4 interconnect pattern.

Reaching CLBs outside the blue area will require more hops. Note especially the "holes" in the blue areas; reaching CLBs in these holes will also require more hops. This complex arrangement impacts speed and increases the complexity of synthesis, place, and route. In irder to address this issue, another ExpressFabric feature is a radically new form of diagonal interconnect that reaches more locations with fewer hops (Fig 3). This diagonally symmetric interconnect pattern is intended to improve both speed and predictability.

3. Diagonally symmetric Virtex-5 interconnect pattern.